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High resolution phase correcting circuit and phase interpolating device

專利號(hào)
US11888486B2
公開(kāi)日期
2024-01-30
申請(qǐng)人
Samsung Electronics Co., Ltd.
發(fā)明人
Jinook Jung; Jaewoo Park; Myoungbo Kwak; Junghwan Choi
IPC分類
H03K5/00; H03K5/01; H03H11/16
技術(shù)領(lǐng)域
signal,clock,phase,clkout,tuning,circuit,may,csb,terminal,delay
地域: Suwon-si

摘要

A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.

說(shuō)明書(shū)

The functions and the operations of the phase correction circuit 4300, the delay circuit 4310, and the first and second fine tuning circuits 4320a and 4320b are similar to those of the phase correction circuit 1300, the delay circuit 1310, and the first and second fine tuning circuit 1320a and 1320b of FIG. 5B, and thus, additional description will be omitted to avoid redundancy.

The first fine tuning circuit 4320a may include the first terminal T1, the second terminal T2, and the third terminal T3. The second fine tuning circuit 4320b may include the fourth terminal T4, the fifth terminal T5, and the sixth terminal T6. A connection relationship of the first fine tuning circuit 4320a and the second fine tuning circuit 4320b is similar to that described with reference to FIG. 5B or 7, and thus, additional description will be omitted to avoid redundancy.

In an embodiment, the first fine tuning circuit 4320a may be implemented with a first variable gain amplifier VGAa. In this case, the first terminal T1 may correspond to an input terminal of the first variable gain amplifier VGAa. The second terminal T2 may correspond to a gain-control terminal of the first variable gain amplifier VGAa. The third terminal T3 may correspond to an output terminal of the first variable gain amplifier VGAa. The first variable gain amplifier VGAa may include the first amplifier parasitic capacitance CAa.

權(quán)利要求

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