High resolution phase correcting circuit and phase interpolating device
摘要
說明書
In an embodiment, the second phase interpolating device 1000b may generate an internal clock signal of the memory device DEV, based on the data signal DQ and the clock signal CLK. The memory device DEV may synchronize the data strobe signal DQS with the data signal DQ based on the internal clock signal.
According to the present disclosure, a high resolution phase correcting circuit and a phase interpolating device, which are capable of fine-turning a phase of a clock signal, may be provided.
While the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.
