FIG. 1 is a block diagram illustrating a phase interpolating device according to an embodiment of the present disclosure. Referring to FIG. 1, a phase interpolating device 1000 may include a decoder DEC and a phase correcting module PCM. The phase correcting module PCM may receive a clock signal CLK and a control signal CS, and may correct the clock signal CLK in response to the control signal CS. For example, the phase correcting module PCM may delay or lead (i.e., advance) a phase of the clock signal CLK, and output a corrected clock signal CCLK.

In an embodiment, the correction for advancing a phase of a clock signal may correspond to the correction for delaying the phase of the clock signal. For example, the correction for delaying the phase of the clock signal may mean adding a positive phase to the phase of the clock signal. The correction for advancing the phase of the clock signal may mean adding a negative phase to the phase of the clock signal.

The decoder DEC may receive the clock signal CLK and a reference signal RCLK. The decoder DEC may generate the control signal CS based on an evaluation of the clock signal CLK and the reference signal RCLK. For example, the decoder DEC may generate the control signal CS based on a phase difference between the clock signal CLK and the reference signal RCLK, and may provide the phase correcting module PCM with the control signal CS thus generated.

In an embodiment, the phase of the corrected clock signal CCLK may be determined based on the phase of the reference signal RCLK. A relationship between the clock signal CLK, the corrected clock signal CCLK, and the reference signal RCLK will be described in detail with reference to FIG. 2.