Background offset calibration of a high-speed analog signal comparator
地域：
Edinburgh
摘要
A background offset calibration system for an analog signal comparator provides low offset without compromising tracking bandwidth. The comparator includes a preamplifier and a decision latch. A switching selectively couples outputs of an analog circuit to the inputs of the preamplifier stage. A state control logic alternatively operates the system in a first phase in which the analog circuit acquires an input signal while the comparator is calibrated, and a second phase in which a comparison is performed by the comparator. In the first phase, the switching circuit disconnects the outputs of the analog circuit from the preamplifier stage and applies a common mode reference to the inputs of the preamplifier. An offset correction circuit determines correction changes from a history of states of the decision latch across multiple sampling cycles. The offset correction circuit adjusts a threshold voltage of the decision latch by applying the correction changes.
說明書
The field of representative embodiments of this disclosure relates to calibration of high-speed comparators as used in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), and in particular to comparator auto-zero calibration systems and techniques.
Analog signal comparators are in common use in data converters, e.g., ADCs and DACs, as well as in other signal acquisition and comparison systems. In particular, for low-power applications, successive-approximation registers are selected as a data converter of choice, because the fundamental active component of such converters is the comparator.
However, comparators suffer from variations in offset voltage due to random element mis-match, and in high-speed devices in particular, mis-match is very problematic due to small device areas employed in high-speed circuits. Solutions to the mis-match problem include conventional auto-zero (AZ) techniques, in which an offset-cancellation voltage is sampled onto capacitors in advance of conversion, and which is used to cancel the comparator offset during the comparator's decision phase. In conventional AZ techniques, the offset contributions from the comparator's output latch are not directly canceled, but are reduced by the gain of the preamplifier stage(s) preceding the latch, therefore a high gain preamplifier is typically required in order to reduce comparator offset variation to required levels. However, as the preamplifier gain is raised, the tracking bandwidth of the converter is correspondingly reduced.
權利要求
What is claimed is:1. A system, comprising:an analog circuit; an analog signal comparator that compares outputs of the analog circuit, the analog signal comparator comprising a preamplifier stage and a decision latch that samples an output of the preamplifier stage to generate an output state of the analog signal comparator; a switching circuit that selectively couples outputs of the analog circuit to inputs of the preamplifier stage of the analog signal comparator; a state control logic that alternatively operates the system in a first phase in which the analog circuit acquires an input signal and the analog signal comparator is being calibrated, and a second phase in which an output of the analog circuit is compared by the analog signal comparator, wherein a sampling cycle comprises operating the system in the first phase and then the second phase, wherein in the first phase, the state control logic controls the switching circuit to disconnect the outputs of the analog circuit from the inputs of the preamplifier stage of the analog signal comparator, and wherein the switching circuit applies a common mode reference to the inputs of the preamplifier stage of the analog signal comparator; and an offset correction circuit that determines an offset correction change dependent on a history of states of an output of the decision latch of the analog signal comparator across multiple sampling cycles of the system, wherein an output of the offset correction circuit is coupled to an offset input of the decision latch of the analog signal comparator to adjust a threshold voltage of the decision latch in conformity with the history of the states of the output of the decision latch. 2. The system of claim 1 , wherein the offset correction circuit determines the offset correction change by applying a non-equal weighting to multiple samples of the output of the decision latch. 3. The system of claim 2 , wherein the offset correction circuit applies a fast-Fourier analysis to the multiple samples of the sampling to determine the offset correction change. 4. The system of claim 1 , wherein the system is an analog-to-digital converter, wherein the first phase is a track/hold phase of the analog-to-digital converter, and wherein the second phase is a conversion phase of the analog-to-digital converter. 5. The system of claim 1 , wherein the system is a built-in-self-test (BIST) circuit within analog circuitry, wherein the first phase is a signal measurement phase of the BIST circuit, and wherein the second phase is an evaluation phase of the BIST circuit. 6. The system of claim 1 , wherein the offset correction circuit comprises a charge pump that applies the offset correction change to a capacitor storing an offset value that is applied to the offset input of the decision latch. 7. The system of claim 6 , wherein the charge pump comprises:a differential integrator; a pair of charging circuits that apply differential reference currents to inputs of the differential integrator with an alternating polarity; and control logic that controls a time of alternation of the polarity of the pair of charging circuits during the second phases of the state control logic, so that the differential integrator is charged in proportion to the determined offset correction change. 8. The system of claim 6 , wherein an active time of the charge pump is varied in conformity with a magnitude of the offset correction change, so that a calibration time of the decision latch across multiple sampling cycles is reduced and residual ripple after calibration is reduced in magnitude. 9. The system of claim 1 , wherein the decision latch of the analog comparator comprises:a pair of cross-coupled latch stages for receiving a clock signal and capturing an output state of the decision latch in response to the clock signal; at least one tail device having an input for receiving the clock signal; a first pair of input ladder stages coupled between corresponding ones of the pair of cross-coupled latch stages and the at least one tail device for receiving the output of the preamplifier stage, whereby the cross-coupled latch stages capture a state determined by conduction of the first pair of input stages in response to the clock signal; and a second pair of input ladder stages coupled between corresponding ones of the pair of cross-coupled latch stages and the at least one tail device for receiving the output of the offset correction circuit, whereby the output of the offset correction circuit adjusts a threshold of the conduction of the first pair of input stages that determines the state captured by the cross-coupled latch stages. 10. The system of claim 9 , wherein the clock signal is a first clock signal, and wherein the at least one tail device comprises:a first tail device coupled to the first pair of input ladder stages and that is controlled by the first clock signal; a second tail device coupled to the second pair of input ladder stages for receiving the second clock signal; and a variable delay circuit having an input coupled to the output of the offset correction circuit and an output providing the second clock signal to the second tail device, whereby the offset correction circuit varies a delay of the variable delay circuit according to the offset correction change. 11. The system of claim 9 , further comprising a digital-to-analog converter having an input coupled to the output of the offset correction circuit for generating a differential offset voltage applied to inputs of the second pair of input ladder stages. 12. A method of calibrating a system including an analog circuit and an analog signal comparator that compares outputs of an analog circuit, the method comprising:alternatively operating the system in a first phase in which the analog circuit acquires an input signal and the analog signal comparator is being calibrated, and a second phase in which the outputs of the analog circuit are compared by the analog signal comparator, wherein a sampling cycle comprises operating the system in the first phase and then the second phase; in the first phase, disconnecting the outputs of the analog circuit from inputs of a preamplifier stage of the analog signal comparator and applying a common mode reference to the inputs of the preamplifier stage of the analog signal comparator while sampling an output of the preamplifier stage of the analog signal comparator with a decision latch of the analog signal comparator; determining an offset correction change dependent on a history of states of an output of the decision latch of the analog signal comparator across multiple sampling cycles of the system; and applying the offset correction change to an offset input of the decision latch of the analog signal comparator to adjust a threshold voltage of the decision latch in conformity with the history of the states of the output of the decision latch. 13. The method of claim 12 , wherein the determining an offset correction change combines multiple samples of the sampling with a non-equal weighting. 14. The method of claim 13 , wherein the determining an offset correction change performs a fast-Fourier analysis of the multiple samples of the sampling to determine the offset correction change. 15. The method of claim 12 , wherein the system is an analog-to-digital converter, wherein the first phase is a track/hold phase of the analog-to-digital converter, and wherein the second phase is a conversion phase of the analog-to-digital converter. 16. The method of claim 12 , wherein the system is a built-in-self-test (BIST) circuit within analog circuitry, wherein the first phase is a signal measurement phase of the BIST circuit, and wherein the second phase is an evaluation phase of the BIST circuit. 17. The method of claim 12 , wherein the applying the offset correction change comprises applying charge to or removing charge from a capacitor storing an offset value that is applied to the offset input of the decision latch. 18. The method of claim 17 , wherein the applying charge to or removing charge from the capacitor comprises:accepting or providing the charge at inputs of a differential integrator by reference currents with an alternating polarity; and controlling a time of alternation of the polarity of the reference currents during the second phases of the system, so that the differential integrator is charged in proportion to the determined offset correction change. 19. The method of claim 17 , wherein an active time of the applying or removing charge is varied in conformity with a magnitude of the offset correction change, so that a calibration time of the decision latch across multiple sampling cycles is reduced and residual ripple after calibration is reduced in magnitude. 20. The method of claim 12 , wherein the decision latch of the analog comparator comprises a pair of cross-coupled latch stages for receiving a clock signal and capturing an output state of the decision latch in response to the clock signal, at least one tail device having an input for receiving the clock signal a first pair of input ladder stages coupled between corresponding ones of the pair of cross-coupled latch stages and the at least one tail device for receiving the output of the preamplifier stage, whereby the cross-coupled latch stages capture a state determined by conduction of the first pair of input stages in response to the clock signal, and a second pair of input ladder stages coupled between corresponding ones of the pair of cross-coupled latch stages and the at least one tail device, and wherein the applying the offset correction change adjusts input voltages of the second pair of input ladder stages to adjust a threshold of the conduction of the first pair of input stages that determines the state captured by the cross-coupled latch stages. 21. The method of claim 20 , wherein the clock signal is a first clock signal, wherein the at least one tail device comprises a first tail device coupled to the first pair of input ladder stages and that is controlled by the first clock signal and a second tail device coupled to the second pair of input ladder stages for receiving the second clock signal, and wherein the applying the correction adjusts a variable delay of the second clock signal with respect to the first clock signal. 22. The method of claim 20 , wherein the applying the correction comprises converting a digital offset correction change to a differential analog offset voltage with a digital-to-analog converter, and applying the differential analog offset voltage to inputs of the second pair of input ladder stages.
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