Referring now to FIG. 3A, a schematic diagram of an example latch circuit 20A that may be used within comparator 14 in SAR ADC 10 of FIG. 2 is shown, in accordance with an embodiment of the disclosure. Example latch circuit 20A has a structure similar to a conventional StrongARM latch, but includes additional inputs that control biasing and offset voltage in example latch circuit 20A. Example latch circuit 20A is formed by two transistor ladders that include pull-up transistors P1A, P2A, P3A and transistors P1B, P2B, P3B for each “arm” of example latch circuit 20A. A clock signal CLK controls conduction of a “tail” or “foot” transistor N4 and also pull-up transistors P1A, P1B, so that when clock signal CLK is raised to a logical high voltage state, e.g., 5 VDC, transistor N4 conducts to permit example latch 20A to evaluate the differential voltage of inputs +in, ?in. Output pull-up transistors P3A, P3B are cross-coupled and a next pair of transistors N3A, N3B down in the ladders are cross-coupled, so that example latch 20A forms a fast bi-stable latch while transistor N4 is turned on, due to a high gain with respect to inputs +in, ?in. Prior to clock signal CLK being asserted, clock signal CLK is in a logical low voltage state, e.g., 0 VDC. A pair of input transistors N1A, N1B receive inputs +in, ?in and track the differential input voltage. When clock signal CLK is raised to the logical high voltage state, the instantaneous strobe current conducted through transistor N4 flows through both “arms” of example latch 20A, but with different strength, according to the difference between voltage at inputs +in, ?in, which due to the positive feedback provided by the cross-coupled pairs of output pull-up transistors P3A, P3B and ladder transistors N3A, N3B, causes the state of output out of example latch 20A to settle to a saturated state determined by the polarity of the differential voltage between inputs +in, ?in. Mismatches between transistors in example latch 20A, and other offsets in the comparator as described above, may be compensated-for by an offset adjustment provision in example latch 20A, in accordance with an embodiment of the disclosure. A transistor N2B receives an offset adjustment voltage V_os and a transistor N2A receives a bias voltage V_b that is generally set to the common mode voltage of inputs +in, ?in, so that the operation of example latch 20A is offset-adjustable, by shifting the operating point of example latch 20A according to the provided offset adjustment voltage V_os and bias voltage V_b, which will change the decision threshold of the above-described evaluation that occurs when tail transistor N4 is activated. Selection of the calibration rate of the background calibration techniques described herein may further be used to cancel 1/f noise of the transistors within example latch 20A and the preamplifier of comparator 14, for example, by selection of a calibration rate higher than twice the knee frequency of the 1/f noise characteristic. While example latch 20A provides an example of a latch circuit that may be used within comparator 14 of in SAR ADC 10 of FIG. 2, other type of latches may be employed and modified according to the above-described example, and such implementations are contemplated in accordance with other embodiments of the disclosure.