Referring now to FIG. 6, a schematic diagram of an example calibration control circuit 50A that may be used to implement calibration control circuit 50 in background-calibrated comparator circuit 14A of FIG. 5, in accordance with an embodiment of the disclosure. A SAR sequencer 60 controls operation of the background calibration process, and may include other control signals for operation of a SAR ADC, such as example SAR ADC 10 of FIG. 2, or for controlling another type of converter or other circuit, and which also may be located external to calibration control circuit 50A, in accordance with other embodiments of the disclosure. A clock signal clk is introduced to a pair of D-latches Q1, Q2, with a delayed version of clock signal clk provided by the output of a delay circuit 20. A third D-latch Q3 is configured to toggle at each assertion of clock signal clk. A logic circuit formed by a logical-AND gate AND1 and a logical-OR gate OR1, provide a reset signal to reset D-latches Q1, Q2, after the leading edge of the delayed version of clock signal clk has caused D-latch Q2 to toggle, asserting a logic signal Late, which occurs after the leading edge of clock signal clk has caused D-latch Q1 to be set, asserting a logic signal Early. D-latches are also reset during every other cycle of clock signal clk when the output of D-latch Q3 is in a logical high state, so that calibration control circuit 50A updates an offset adjustment voltage +V_os, during, for example, the track/hold phase of SAR ADC 10. A set of logical-AND gates AND2-AND5, a pair of logical-OR gates OR2, OR3, and an inverter INV1, form a multiplexer that selects one of logic signal Early or logic signal Late to control a positive charge pump switch S20, and the other one of logic signal Early or logic signal Late to control a negative charge pump switch S21, according to a control signal polarity provided by SAR sequencer 60. A current source 110 and a current source I11, provide current pulses of positive or negative polarity, respectively, when switch S20 or switch S21 is activated, which cause incremental changes in offset adjustment voltage +V_os, which is held by a capacitor C10. A control signal Preamp ctl configures the preamplifier of the comparator being calibrated, for example by operating switches S10A, S10B, S11A and S11B of comparator 14A of FIG. 5, to force the inputs of the preamplifier to common-mode voltage V_cm during calibration. The operation of example calibration control circuit 50A produces a pulse at every calibration cycle, which has a polarity as determined by a logical circuit or micro-program within SAR sequencer that, in the depicted embodiment, implements a filter 62 that accumulates decisions provided from the output of the comparator as input signal decision to SAR sequencer 60 over multiple calibration cycles to determine control signal polarity, which, in turn, determines the direction in which the charge pump updates offset adjustment voltage +V_os. The width of the pulses is determined by a time delay Δt of delay circuit 20, which may be a fixed time delay, or may be a variable time delay controlled by a control value T_ADJ provided from SAR sequencer 60 to alter the rate of change of offset adjustment voltage +V_os according to the decision history accumulated by filter 62. Filter 62 may be a digital finite impulse response (FIR) filter that processes the comparator decision history, which may then be used to control the active time of the charge pump by adjusting control value T_ADJ. The selection of a response for filter 62 may be flexible, within the constraint that the calibration control loop remains stable, and an optimized FIR response may minimize the initial transient introduced by the calibration intervals. An example FIR response may be a simple moving average of calibration decisions, and the active time Δt of the charge pump may have finite steps that may be determined based on a moving average output of filter 62. When offset adjustment voltage V_os converges to a final target voltage, the moving average output of filter 62 may be, for example 0.5, and active time Δt may be at a minimum in order to minimize ripple in offset adjustment voltage V_os after the calibration loop has settled to a proper offset compensation value. When the deviation of the output of filter 62 from the target midpoint value of 0.5 is significant, a longer active time Δt may be used to reduce the settling time of the calibration loop response. The control of control value T_ADJ may be flexible and may include whatever resolution is desired, but generally a 2-bit adjustment (4-value range) may be sufficient. As an alternative to the FIR filter example described above, filter 62 may be implemented with a fast-Fourier transform (FFT) that allows analysis in the frequency domain to compute the offset adjustment voltage V_os across multiple cycles, with unequal weighting applied to the terms at different samples of the FFT to emphasize samples nearer in time to the present calibration interval. Similarly, the FIR filter may have tap coefficients weighted in a similar manner.