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Background offset calibration of a high-speed analog signal comparator

專利號
US11888492B2
公開日期
2024-01-30
申請人
CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.(US TX Austin)
發(fā)明人
Jianping Wen; John L. Melanson
IPC分類
H03M1/06
技術(shù)領(lǐng)域
comparator,latch,offset,sar,voltage,circuit,vos,analog,in,signal
地域: Edinburgh

摘要

A background offset calibration system for an analog signal comparator provides low offset without compromising tracking bandwidth. The comparator includes a preamplifier and a decision latch. A switching selectively couples outputs of an analog circuit to the inputs of the preamplifier stage. A state control logic alternatively operates the system in a first phase in which the analog circuit acquires an input signal while the comparator is calibrated, and a second phase in which a comparison is performed by the comparator. In the first phase, the switching circuit disconnects the outputs of the analog circuit from the preamplifier stage and applies a common mode reference to the inputs of the preamplifier. An offset correction circuit determines correction changes from a history of states of the decision latch across multiple sampling cycles. The offset correction circuit adjusts a threshold voltage of the decision latch by applying the correction changes.

說明書

? "\[RightBracketingBar]" ( D 3 , D 2 ) : Δ ? T 2 ? "\[LeftBracketingBar]" FIR [ D ? ( n - N + 1 : n ) ] - 0.5 ? "\[RightBracketingBar]" D 3 : Δ ? T min

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