FIG. 11 illustrates further details of the calibration control of FIG. 10 during the initial transient of adjustment to the value of offset adjustment voltage Vos. Time T0 occurs at the end of a comparator auto-zero phase of one calibration cycle, when the comparator makes a calibration decision at the rising edge of the clock signal indicated by waveform 115. In the depicted example, the decision, shown as waveform 116, is a logical “1”, and the charge pump charges the output capacitor(s) to an increased step in offset adjustment voltage Vos voltage shown by waveform 114. Subsequently, the SAR ADC enters a successive approximation (evaluation) phase to convert the current sample. Subsequent intervals show pairs of calibration/evaluation phases, as offset adjustment voltage Vos voltage increases as the calibration control loop converges. Waveform 111 is clock signal clk, waveform 112 is the calibration phase command signal, and waveform 113 is the SAR error, which approaches zero, illustrating the conversion evaluation successively approximating the target digital output code. FIG. 12 illustrates an FFT of the output of SAR ADC 10. Output distortion is dominated by the third harmonic 122, which is ?80 dB below the level of the signal amplitude 121, which is sufficient for implementation of a 12-bit ADC.
