In some example embodiments, the decision latch of the analog comparator may include a pair of cross-coupled latch stages for receiving a clock signal and capturing an output state of the decision latch in response to the clock signal, at least one tail device having an input for receiving the clock signal, a first pair of input ladder stages coupled between corresponding ones of the pair of cross-coupled latch stages and the at least one tail device for receiving the output of the preamplifier stage, whereby the cross-coupled latch stages capture a state determined by conduction of the first pair of input stages in response to the clock signal, and a second pair of input ladder stages coupled between corresponding ones of the pair of cross-coupled latch stages and the at least one tail device for receiving the output of the offset correction circuit, whereby the output of the offset correction circuit adjusts a threshold of the conduction of the first pair of input stages that determines the state captured by the cross-coupled latch stages. In some example embodiments, the clock signal may be a first clock signal, and the at least one tail device may include a first tail device coupled to the first pair of input ladder stages and that is controlled by the first clock signal, a second tail device coupled to the second pair of input ladder stages for receiving the second clock signal, and a variable delay circuit having an input coupled to the output of the offset correction circuit and an output providing the second clock signal to the second tail device, whereby the offset correction circuit varies a delay of the variable delay circuit according to the offset correction change. In some example embodiments, the system may further include a digital-to-analog converter having an input coupled to the output of the offset correction circuit for generating a differential offset voltage applied to inputs of the second pair of input ladder stages.