FIG. 16 illustrates various components that may be utilized in a UE 1802. The UE 1802 described in connection with FIG. 16 may be implemented in accordance with the UE 102 described in connection with FIG. 1. The UE 1802 includes a processor 1803 that controls operation of the UE 1802. The processor 1803 may also be referred to as a central processing unit (CPU). Memory 1805, which may include read-only memory (ROM), random access memory (RAM), a combination of the two or any type of device that may store information, provides instructions 1807a and data 1809a to the processor 1803. A portion of the memory 1805 may also include non-volatile random-access memory (NVRAM). Instructions 1807b and data 1809b may also reside in the processor 1803. Instructions 1807b and/or data 1809b loaded into the processor 1803 may also include instructions 1807a and/or data 1809a from memory 1805 that were loaded for execution or processing by the processor 1803. The instructions 1807b may be executed by the processor 1803 to implement the methods described above.
The UE 1802 may also include a housing that contains one or more transmitters 1858 and one or more receivers 1820 to allow transmission and reception of data. The transmitter(s) 1858 and receiver(s) 1820 may be combined into one or more transceivers 1818. One or more antennas 1822a-n are attached to the housing and electrically coupled to the transceiver 1818.
