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Devices and methods for the detection and localization of fault injection attacks

專利號(hào)
US11930098B2
公開日期
2024-03-12
申請人
SECURE-IC SAS(FR Cesson-Sevigne)
發(fā)明人
Rachid Dafali
IPC分類
H04L9/40; G06F7/58; H04L9/00
技術(shù)領(lǐng)域
signal,attacks,clock,random,digital,manager,circuit,values,or,receiver
地域: Cesson-Sevigne

摘要

A device for detecting perturbation attacks performed on a digital circuit is provided. The device comprises: a first metallic layer and a second metallic layer arranged on the digital circuit, the first metal layer comprising a plurality of signal transmission lines routed horizontally, the second metal layer comprising a plurality of signal transmission lines routed vertically, the device comprising one or more transmitter buffers and one or more receiver buffers, a transmitter buffer and a receiver buffer being connected by each signal transmission line; a random number generator configured to generate random signal values; the device further comprising a transmitter manager connected to one or more transmitter buffers and a receiver manager connected to one or more receiver buffers, wherein: the transmitter manager is configured to transmit random signal values generated by the random number generator over the signal transmission lines of the first metallic layer and the second metallic layer, the receiver manager is configured to receive random signal values from the transmitter manager through the one or more receiver buffers connected to the receiver manager, measure a transmission time corresponding to a time of transmission of the received random signal values, and compare the transmission time to a predefined timing interval to detect perturbation attacks.

說明書

According to some embodiments, the transmission of the random signal values over the signal transmission lines of the first metallic layer 11 and the second metallic layer 13 may be performed at each rising edge of the system clock. In such embodiments, the random number generator 15 may be configured to update the random signal values to be transmitted to the transmitter manager 17 and the receiver manager 19 at each rising edge of the system clock. Upon receiving the updated random signal values, the transmitter manager 17 may be configured to transmit the updated random signal values at the rising edge of the system clock over the signal transmission lines of the first metallic layer 11 and the second metallic layer 13. The receiver manager 19 may be configured to receive the updated random signal values during the rising edge of the system clock from the random number generator 15, to store the updated random signal values, and to initialize a counter at each rising edge of the system clock.

According to some embodiments in which the transmission time required for transmitting the random signal values is less than or equal to one system clock cycle, the receiver manager 19 may use an internal clock with a frequency higher than the frequency of the system clock to define the timing interval I=[t0, t1] represented by a first threshold t0 and a second threshold t1 and defined, in such embodiments, by the number of internal clock cycles needed to transmit the random signal values through the signal transmission lines.

When using an internal clock cycle for measuring the signals transmission time, the receiver manager 19 may be configured, at each rising edge of the internal clock, to:

權(quán)利要求

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