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Devices and methods for the detection and localization of fault injection attacks

專利號
US11930098B2
公開日期
2024-03-12
申請人
SECURE-IC SAS（FR Cesson-Sevigne）
發(fā)明人
Rachid Dafali
IPC分類
H04L9/40; G06F7/58; H04L9/00
技術(shù)領(lǐng)域
signal,attacks,clock,random,digital,manager,circuit,values,or,receiver
地域： Cesson-Sevigne

摘要

A device for detecting perturbation attacks performed on a digital circuit is provided. The device comprises: a first metallic layer and a second metallic layer arranged on the digital circuit, the first metal layer comprising a plurality of signal transmission lines routed horizontally, the second metal layer comprising a plurality of signal transmission lines routed vertically, the device comprising one or more transmitter buffers and one or more receiver buffers, a transmitter buffer and a receiver buffer being connected by each signal transmission line; a random number generator configured to generate random signal values; the device further comprising a transmitter manager connected to one or more transmitter buffers and a receiver manager connected to one or more receiver buffers, wherein: the transmitter manager is configured to transmit random signal values generated by the random number generator over the signal transmission lines of the first metallic layer and the second metallic layer, the receiver manager is configured to receive random signal values from the transmitter manager through the one or more receiver buffers connected to the receiver manager, measure a transmission time corresponding to a time of transmission of the received random signal values, and compare the transmission time to a predefined timing interval to detect perturbation attacks.

說明書

  • if the receiver manager 19 determines that the counter is lower than the first threshold t0 and that the random signal values transmitted through the signal transmission lines during the current system clock cycle are different from the random signal values transmitted through the signal transmission lines during the precedent system clock cycle, this means that the signal values change before the minimum delay of the transmission computed during the design phase, and so the signals were accelerated due to an external manipulation, or
  • if the receiver manager 19 determines that the counter is higher than the second threshold t1 and that the random signal values transmitted through the signal transmission lines during the current system clock cycle are different from the random signal values transmitted through the signal transmission lines during the precedent system clock cycle, this means that the signal values change after the maximum delay of the transmission computed during the design phase, thus indicating that the signal values were slowed or perturbed after a correct transmission, or
  • if the receiver manager 19 determines that the random signal values transmitted through the signal transmission lines change more than two times during one system clock cycle, this means that the values of the transmitted signals were changed many times during the transmission and that the digital circuit 1 is under an external manipulation.

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