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Devices and methods for the detection and localization of fault injection attacks

專利號(hào)
US11930098B2
公開日期
2024-03-12
申請(qǐng)人
SECURE-IC SAS(FR Cesson-Sevigne)
發(fā)明人
Rachid Dafali
IPC分類
H04L9/40; G06F7/58; H04L9/00
技術(shù)領(lǐng)域
signal,attacks,clock,random,digital,manager,circuit,values,or,receiver
地域: Cesson-Sevigne

摘要

A device for detecting perturbation attacks performed on a digital circuit is provided. The device comprises: a first metallic layer and a second metallic layer arranged on the digital circuit, the first metal layer comprising a plurality of signal transmission lines routed horizontally, the second metal layer comprising a plurality of signal transmission lines routed vertically, the device comprising one or more transmitter buffers and one or more receiver buffers, a transmitter buffer and a receiver buffer being connected by each signal transmission line; a random number generator configured to generate random signal values; the device further comprising a transmitter manager connected to one or more transmitter buffers and a receiver manager connected to one or more receiver buffers, wherein: the transmitter manager is configured to transmit random signal values generated by the random number generator over the signal transmission lines of the first metallic layer and the second metallic layer, the receiver manager is configured to receive random signal values from the transmitter manager through the one or more receiver buffers connected to the receiver manager, measure a transmission time corresponding to a time of transmission of the received random signal values, and compare the transmission time to a predefined timing interval to detect perturbation attacks.

說(shuō)明書

In step 39, one or more perturbation attacks may be detected and localized by comparing the measured transmission time to a predefined timing interval I.

According to some embodiments, the predefined timing interval I may be previously determined through a set of simulations performed during the design phase of the digital circuit 1, target of one or more perturbation attacks. The set of simulations may be performed to determine, for each of one or more process corners, the timing interval corresponding to the number of clock cycles required to carry signals through the signal transmission lines of the digital circuit 1.

According to some embodiments, the timing interval may depend on one or more parameters comprising the length of the signal transmission lines, temperature, voltage, and a load of the power supply charging the digital circuit 1.

The predefined timing interval I=[t0, t1] may be represented by a first threshold denoted by t0 corresponding to a minimum timing value and a second threshold t1 corresponding to a maximum timing value. Using the simulations performed during the design phase to determine the timing interval, the first and second thresholds may be previously determined for one or more process corners.

權(quán)利要求

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