According to some embodiments in which the transmission time required for transmitting the random signal values is less than or equal to one system clock cycle, an internal clock with a frequency higher than the frequency of the system clock may be used at step 39 in order to define the timing interval I=[t₀, t₁] represented by a first threshold t₀ and a second threshold t₁, the timing interval corresponding in such embodiments to the number of internal clock cycles needed to transmit the random signal values through the signal transmission lines.

In such embodiments, step 37 may further comprise, performing one or more of the following steps at each rising edge of the internal clock:

• • incrementing the counter;
  • comparing the counter to the first threshold t₀ and a second threshold t₁;
  • reading the random signal values transmitted through the signal transmission lines and received at step 37;
  • comparing the received random signal values to the stored random signal values updated at the rising edge of the current system clock cycle; and
  • comparing the received random signal values that have been transmitted through the signal transmission lines during the current system clock cycle to the random signal values transmitted through the signal transmission lines during the precedent system clock cycle.

Depending on the comparisons results, one or more perturbation attacks may be detected in step 39: