Semiconductor structure and method of manufacturing same
地域：
Hefei
摘要
The present application relates to a semiconductor structure and a method of manufacturing the same. The method includes: providing a substrate; forming a bitline contact hole located in the substrate, and a non-metal conductive layer with which a surface of the substrate is covered and the bitline contact hole is filled, the non-metal conductive layer provided with a first opening therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer, with which a surface of the non-metal conductive layer is covered; forming an insulation layer, with which a surface of the metal conductive layer surface is covered; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure.
說明書
The present application is a continuation of PCT/CN2021/100787, filed on Jun. 18, 2021, which claims priority to Chinese Patent Application No. 2020106847515, entitled “SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME” and filed to the Patent Office of the People's Republic of China on Jul. 16, 2020, the entire contents of which are incorporated herein by reference.
The present application relates to the field of semiconductor manufacturing technologies, in particular to a semiconductor structure and a method of manufacturing the same.
In a semiconductor structure, a bitline structure is of a laminated construction of a cap layer (an insulation layer), a metal conductive layer, and a non-metal conductive layer disposed from top to bottom as a stack, wherein the metal conductive layer and the non-metal conductive layer form a bitline of the bitline structure. In order to mitigate a phenomenon of electric leakage between the bitlines, the bitline in a current semiconductor structure has a small width in a bitline contact hole, and the reduction in width causes an increased contact resistance between the bitline and an active region (i.e., a bitline contact resistance); besides, the bitline has a great width on a surface of a substrate and thus, occupies partial space of a node contact window and causes an increased contact resistance between the node contact window and the active region (i.e., a node contact resistance), thereby affecting the quality of the semiconductor structure.
權(quán)利要求
What is claimed is:1. A method of manufacturing a semiconductor structure, comprising:providing a substrate; forming a bitline contact hole located in the substrate, and forming a non-metal conductive layer to cover a surface of the substrate and fill the bitline contact hole, the non-metal conductive layer having a first opening formed therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer to cover a surface of the non-metal conductive layer; forming an insulation layer to cover a surface of the metal conductive layer; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure; wherein the metal conductive layer and the non-metal conductive layer collectively form a bitline, and the bitline located in the bitline contact hole has a width not less than that of the bitline located outside of the bitline contact hole; wherein forming the bitline contact hole and the non-metal conductive layer comprises: forming a first sublayer of non-metal conductive material on the substrate; etching the first sublayer of non-metal conductive material and the substrate to form the bitline contact hole, a retained first sublayer of non-metal conductive material serving as a first sublayer of the non-metal conductive layer; and forming a second sublayer of the non-metal conductive layer to cover the bitline contact hole, and a top of the second sublayer of the non-metal conductive layer is lower than a top of the first sublayer of the non-metal conductive layer, the first and second sublayers of the non-metal conductive layer collectively forming the non-metal conductive layer. 2. The method of manufacturing the semiconductor structure according to claim 1 , wherein in the bitline structure, the bitline located in the bitline contact hole has a width greater than that of the bitline outside of the bitline contact hole. 3. The method of manufacturing the semiconductor structure according to claim 1 , wherein etching the first sublayer of non-metal conductive material and the substrate to form the bitline contact hole comprises:forming a first hard mask layer on the first sublayer of non-metal conductive material, the first hard mask layer having a first graphical target pattern, the first graphical target pattern defining the bitline contact hole; and etching, based on the first hard mask layer, the first sublayer of non-metal conductive material and the substrate to form the bitline contact hole. 4. The method of manufacturing the semiconductor structure according to claim 3 , wherein forming the second sublayer of the non-metal conductive layer comprises:forming a second sublayer of non-metal conductive material to fill the bitline contact hole and to cover a surface of the first hard mask layer; and etching the second sublayer of non-metal conductive material based on the first hard mask layer until a height difference between a top of the first sublayer of non-metal conductive material and a top of the second sublayer of non-metal conductive material equals to a preset value, a retained second sublayer of non-metal conductive material serving as the second sublayer of the non-metal conductive layer. 5. The method of manufacturing the semiconductor structure according to claim 1 , wherein an atomic layer deposition technology is used to form the metal conductive layer. 6. The method of manufacturing the semiconductor structure according to claim 1 , wherein forming the metal conductive layer comprises:forming a metal barrier material layer to cover the surface of the non-metal conductive layer; and forming a metal material layer to cover a surface of the metal barrier material layer. 7. The method of manufacturing the semiconductor structure according to claim 1 , wherein etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form the bitline structure comprises:forming a second hard mask layer on the insulation layer, the second hard mask layer having a second graphical target pattern, the second graphical target pattern defining the bitline structure; with the metal conductive layer serving as an etching stop layer, using the second hard mask layer as a mask to etch the insulation layer to transfer the second graphical target pattern to the insulation layer; removing the second hard mask layer; and with the insulation layer serving as a mask, etching the metal conductive layer and the non-metal conductive layer to form the bitline structure. 8. The method of manufacturing the semiconductor structure according to claim 7 , wherein using the insulation layer as the mask to etch the metal conductive layer and the non-metal conductive layer comprises:with a metal barrier material layer serving as an etching stop layer, using the insulation layer as a mask to etch metal material to transfer the second graphical target pattern to the metal conductive layer; with the non-metal conductive layer serving as an etching stop layer, using the insulation layer as the mask to etch the metal barrier material layer to transfer the second graphical target pattern to the metal barrier material layer; and using the insulation layer as the mask to etch the non-metal conductive layer to transfer the second graphical target pattern to the non-metal conductive layer. 9. The method of manufacturing the semiconductor structure according to claim 1 , wherein a polycrystalline material is used to manufacture a non-metal conductive material layer. 10. The method of manufacturing the semiconductor structure according to claim 9 , wherein an etching gas containing Cl2 is used to etch the non-metal conductive layer. 11. The method of manufacturing the semiconductor structure according to claim 1 , wherein the method further comprises:before the bitline contact hole and the non-metal conductive layer are formed, forming a dielectric layer to cover the surface of the substrate.
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