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Semiconductor structure and method of manufacturing same

專利號(hào)
US11930635B2
公開(kāi)日期
2024-03-12
申請(qǐng)人
CHANGXIN MEMORY TECHNOLOGIES, INC.(CN Hefei)
發(fā)明人
Zhongming Liu; Jia Fang
IPC分類
H01L27/108; H10B12/00
技術(shù)領(lǐng)域
bitline,layer,conductive,metal,sublayer,mask,material,non,hole,contact
地域: Hefei

摘要

The present application relates to a semiconductor structure and a method of manufacturing the same. The method includes: providing a substrate; forming a bitline contact hole located in the substrate, and a non-metal conductive layer with which a surface of the substrate is covered and the bitline contact hole is filled, the non-metal conductive layer provided with a first opening therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer, with which a surface of the non-metal conductive layer is covered; forming an insulation layer, with which a surface of the metal conductive layer surface is covered; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure.

說(shuō)明書

Step 2: etching the first sublayer of non-metal conductive material 310a and the substrate 100 to form the bitline contact hole 200, the retained first sublayer of non-metal conductive material 310a serving as a first sublayer 310 of the non-metal conductive layer. Referring to FIGS. 4 and 5, in one of the embodiments, the step of etching the first sublayer of non-metal conductive material 310a and the substrate 100 to form the bitline contact hole 200 includes: forming a first hard mask layer on the first sublayer of non-metal conductive material 310a, the first hard mask layer having a first graphical target pattern, the first graphical target pattern defining the bitline contact hole 200; etching, based on the first hard mask layer, the first sublayer of non-metal conductive material 310a and the substrate 100 to form the bitline contact hole 200.

權(quán)利要求

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