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Semiconductor structure and method of manufacturing same

專利號
US11930635B2
公開日期
2024-03-12
申請人
CHANGXIN MEMORY TECHNOLOGIES, INC.(CN Hefei)
發(fā)明人
Zhongming Liu; Jia Fang
IPC分類
H01L27/108; H10B12/00
技術領域
bitline,layer,conductive,metal,sublayer,mask,material,non,hole,contact
地域: Hefei

摘要

The present application relates to a semiconductor structure and a method of manufacturing the same. The method includes: providing a substrate; forming a bitline contact hole located in the substrate, and a non-metal conductive layer with which a surface of the substrate is covered and the bitline contact hole is filled, the non-metal conductive layer provided with a first opening therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer, with which a surface of the non-metal conductive layer is covered; forming an insulation layer, with which a surface of the metal conductive layer surface is covered; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure.

說明書

In this embodiment, the metal conductive layer 400 is of a laminated construction, including the metal barrier material layer 410 and the metal material layer 420 disposed sequentially from bottom to top. The metal barrier material layer 410 and the metal material layer 420 may be formed by a stack of any one or combination of titanium nitride, titanium, tungsten silicide or a tungsten nitride and tungsten; wherein the metal barrier material layer 410 is formed using any one or combination of titanium nitride, titanium, tungsten silicide, tungsten nitride or tungsten silicon nitride. Besides, the metal conductive layer 400 may also be formed using other metals, metal nitride, metal silicide, and metal silicon nitride.

權(quán)利要求

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