The bitline structure 900 includes a non-metal conductive layer 300, a metal conductive layer 400, and an insulation layer 500 disposed from bottom to top as a stack, wherein the non-metal conductive layer 300 is sequentially and alternately located on a surface of the semiconductor substrate 100 and a bottom of the bitline contact hole 200; wherein the metal conductive layer 400 and the non-metal conductive layer 300 collectively form a bitline, and the bitline located in the bitline contact hole has a width no less than the bitline located outside of the bitline contact hole.

It can be understood that in this embodiment, the semiconductor structure is manufactured by using the method according to the embodiments described above; with the formation of the non-metal conductive layer 300 having a first opening K1 and the formation of the metal conductive layer 400 having a second opening K2 during the manufacturing procedure, such that the duration of etching the metal conductive layer 400 located outside of the bitline contact hole 200 is increased in the course of forming the bitline structure 900 by the etching process, and the metal conductive layer 400 located outside of the bitline contact hole 200 has a width less than or equal to the bottom of the metal conductive layer 400 located in the bitline contact hole 200, which is beneficial to increase the area of the node contact window and the bitline structure 900 contacting the active region, reducing the node contact resistance and the bitline contact resistance, and improving the quality of the semiconductor structure.