Memory array and methods used in forming a memory array
地域：
ID
ID Boise
摘要
A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.
說明書
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
This patent resulted from a divisional of U.S. patent application Ser. No. 16/288,982 filed Feb. 28, 2019, which is hereby incorporated by reference herein.
Embodiments disclosed herein pertain to memory arrays and to methods used in forming a memory array.
Memory is one type of integrated circuitry and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digit lines (which may also be referred to as bitlines, data lines, or sense lines) and access lines (which may also be referred to as wordlines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line.
Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.
權(quán)利要求
The invention claimed is:1. A memory array comprising:a vertical stack comprising: a conductive tier; an insulator tier above the conductive tier; a first stack comprising at least three select gate tiers above the insulator tier, one of the select gate tiers comprising conducting metal material, another of the select gate tiers comprising conductively-doped semiconductive material, the first stack comprising more conducting metal material tiers than conductively-doped semiconductive material tiers; a second stack comprising vertically-alternating insulative tiers and wordline tiers above the first stack, the wordline tiers comprising gate regions of individual memory cells, individual of the gate regions comprising part of a wordline in individual of the wordline tiers; channel material extending elevationally through the insulative tiers, the wordline tiers, the one select gate tier, and the another select gate tier, the channel material being a homogenous material comprising doped crystalline semiconductor material that extends continuously through the insulative tiers is directly physically contacting and directly electrically coupled with conductive material in the conductive tier; the individual memory cells comprising a memory structure between the individual gate regions and the channel material; the memory structure comprising a charge-blocking region laterally inward of the individual gate regions, a storage region laterally inward of individual of the charge-blocking regions, and insulative charge-passage material laterally inward of individual of the storage regions; a select gate in the one select gate tier and in the another select gate tier, the select gate comprising the conducting metal material in the one select gate tier and the conductively-doped semiconductive material in the another select gate tier; and an insulating material vertically between and vertically separating the conducting metal material and the conductively-doped semiconductive material proximate the channel material, the conducting metal material in the one select gate tier and the conductively-doped semiconductive material in the another select gate tier being directly coupled to one another distal the channel material. 2. The memory array of claim 1 wherein the conductively-doped semiconductive material is vertically thicker than the conducting metal material. 3. The memory array of claim 1 wherein the conducting metal material is above the conductively-doped semiconductive material. 4. The memory array of claim 1 wherein at least one of the conductively-doped semiconductive material tiers is vertically thicker than each of the conducting metal material tiers. 5. The memory array of claim 4 wherein the at least one of the conductively-doped semiconductive material tiers is at least vertically twice as thick than each of the conducting metal material tiers. 6. The memory array of claim 1 wherein the first stack comprises at least four select gate tiers comprising vertically-alternating conducting metal material and conductively-doped semiconductive material. 7. The memory array of claim 6 wherein the conductively-doped semiconductive material in at least one of the conductively-doped semiconductive material tiers is vertically thicker than the conducting metal material in each of the conducting metal material tiers. 8. The memory array of claim 7 wherein the conductively-doped semiconductive material in each of the conductively-doped semiconductive material tiers is vertically thicker than the conducting metal material in each of the conducting metal material tiers. 9. The memory array of claim 1 wherein the conductively-doped semiconductive material comprises conductively-doped polysilicon. 10. The memory array of claim 1 comprising NAND. 11. The memory array of claim 10 comprising CMOS under array circuitry electrically coupled to at least one of (a) the conductive tier, (b) the select gate tier, and (c) the wordlines. 12. The memory array of claim 1 wherein the conducting metal material in the one select gate tier comprises elemental W; at least one of Al2O3 and HfOx being above, below, and aside the elemental W. 13. The memory array of claim 1 wherein the one select gate tier is above the another select gate tier, the conducting metal material in the one select gate tier comprises elemental W and the conductively-doped semiconductive material in the another select gate tier comprises conductively-doped polysilicon. 14. The memory array of claim 1 wherein the one select gate tier is below the another select gate tier, the conducting metal material in the one select gate tier comprises elemental W and the conductively-doped semiconductive material in the another select gate tier comprises conductively-doped polysilicon. 15. The memory array of claim 1 wherein the first stack comprises at least three select gate tiers, a first of the at least three select gate tiers being below a second of the at least three select gate tiers, a third of the at least three select gate tiers being above the second select gate tier, the first and third select gate tiers comprising the conducting metal material which comprises elemental W, the second select gate tier comprising the conductively-doped semiconductive material which comprises conductively-doped polysilicon. 16. A memory array comprising:a vertical stack comprising: a conductive tier; an insulator tier above the conductive tier; a first stack comprising at least three select gate tiers above the insulator tier, one of the select gate tiers comprising conducting metal material, another of the select gate tiers comprising conductively-doped semiconductive material; and a second stack comprising vertically-alternating insulative tiers and wordline tiers above the first stack, the wordline tiers comprising gate regions of individual memory cells, individual of the gate regions comprising part of a wordline in individual of the wordline tiers; channel material extending elevationally through the insulative tiers, the wordline tiers, the one select gate tier, and the another select gate tier and is directly electrically coupled with conductive material in the conductive tier; the individual memory cells comprising a memory structure between the individual gate regions and the channel material; the memory structure comprising a charge-blocking region laterally inward of the individual gate regions, a storage region laterally inward of individual of the charge-blocking regions, and insulative charge-passage material laterally inward of individual of the storage regions; a select gate in the one select gate tier and in the another select gate tier, the select gate comprising the conducting metal material in the one select gate tier and the conductively-doped semiconductive material in the another select gate tier; and an insulating material vertically between and vertically separating the conducting metal material and the conductively-doped semiconductive material proximate the channel material, the conducting metal material in the one select gate tier and the conductively-doped semiconductive material in the another select gate tier being directly coupled to one another distal the channel material, and wherein the conducting metal material is below the conductively-doped semiconductive material.
意見反饋
使用該功能遇到問題
該功能需要專業(yè)版企業(yè)版VIP權(quán)限，您可以：
您也可以聯(lián)系官方QQ: 2157717237 電話: 13264338900