Referring to FIGS. 13-15, conducting material 48 and insulating material 53 have been removed from individual trenches 40. Such has resulted in formation of wordlines 29 and elevationally-extending strings 49 of individual transistors and/or memory cells 56. Such removing may be conducted by etching, for example by one or both of anisotropic etching or isotropic etching. In one isotropic etching example, trenches 40 can be formed to be wider than the vertical depth of individual wordline tiers 22 (not shown). Conducting material 48 can then be deposited to a thickness that less-than-fills trenches 40 (not shown), for example to leave a laterally-centered void space within trenches 40 (not shown). Thereafter, such conducting material can be isotropically etched within the void space to form wordlines 29 that are separated as is shown by the depicted FIGS. 13 and 14 cross-sections. Approximate locations of transistors and/or memory cells 56 are indicated with a bracket in FIG. 15 and some with dashed outlines in FIGS. 13 and 14, with transistors and/or memory cells 56 being essentially ring-like or annular in the depicted example. Conducting material 48 may be considered as having terminal ends 50 (FIG. 15) corresponding to control-gate regions 52 of individual transistors and/or memory cells 56. Control-gate regions 52 in the depicted embodiment comprise individual portions of individual wordlines 29. Materials 30, 32, and 34 may be considered as a memory structure 65 that is laterally between control-gate region 52 and channel material 36.