In the example embodiment, a select gate (e.g., SGS) is ultimately formed that is in the one select gate tier 14 and in the another select gate tier 21, with such select gate comprising conducting material 48 in the one select gate tier 14 and conductor material 17 in the another select gate tier 21. When insulating material 53 is vertically between and vertically separates a conducting metal material 48 and a conductively-doped semiconductive material 17 proximate channel material 36, such insulating material may be sufficiently thin and leaky that such materials 48 and 17 are effectively directly electrically coupled together. Further and regardless, conducting material 48 in the one select gate tier 14 and conductor material 17 in the another select gate tier 21 may be directly coupled to one another distal the channel material, for example at edges of the array as schematically shown by an interconnect 54 in FIG. 14.

Referring to FIGS. 16 and 17, a material 57 (dielectric and/or silicon-containing such as undoped polysilicon) has been formed in individual trenches 40.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used with respect to the above-described embodiments.

The above example processing shows forming conducting material 48 of individual wordlines 29 in wordline tiers 22 after forming channel material 36. Alternately, and by way of example only, the conducting material of the individual wordlines in the wordline tiers may be formed before forming channel material 36, including even before forming channel openings 25.