In one embodiment, a memory array (e.g., 12) comprises a vertical stack (e.g., 100) comprising a conductive tier (e.g., 16), an insulator tier (e.g., 13) above the conductive tier, and a first stack (e.g., 15) above the insulator tier. The first stack comprises multiple select gate tiers (e.g., 21, 14) above the insulator tier. One of the select gate tiers (e.g., 14) comprises conducting metal material and another of the select gate tiers (e.g., 21) comprises conductively-doped semiconductive material (e.g., 17). A second stack (e.g., 18) comprises vertically-alternating insulative tiers (e.g., 20) and wordline tier (e.g., 22) and is above the first stack. The wordline tiers comprise gate regions (e.g., 52) of individual memory cells (e.g., 56), with individual of the gate regions comprising part of a wordline (e.g., 29) in individual of the wordline tiers. Channel material (e.g., 36) extends elevationally through the insulative tiers, the wordline tiers, the one select gate tier, and the another select gate tier and is directly electrically coupled with conductive material (e.g., 19) in the conductive tier. The individual memory cells comprise a memory structure (e.g., 65) between the individual gate regions and the channel material. The memory structure comprises a charge-blocking region (e.g., 30) laterally inward of the individual gate regions, a storage region (e.g., 32) laterally inward of individual of the charge-blocking regions, and insulative charge-passage material (e.g., 34) laterally inward of individual of the storage regions. A select gate (e.g., SGS) is in the one select gate tier (e.g., 14) and in the another select gate tier (e.g., 21). The select gate comprises the conducting metal material (e.g., 48) in the one select gate tier (e.g., 14) and the conductively-doped semiconductive material (e.g., 17) in the another select gate tier (e.g., 21)