In one embodiment, the conductively-doped semiconductive material is vertically thicker than the conducting metal material, and in one embodiment the conducting metal material is above the conductively-doped semiconductive material. In one embodiment, the conductively-doped semiconductive material comprises conductively-doped polysilicon. In one embodiment, the memory array comprises NAND, and in one embodiment comprises CMOS under array circuitry electrically coupled to at least one of (a) the conductive tier, (b) the select gate tier, and (c) the wordlines. In one embodiment, the memory array comprises an insulating material (e.g., 53) vertically between and vertically separating the conducting metal material and the conductively-doped semiconductive material proximate the channel material, with the conducting metal material in the one select gate tier and the conductively-doped semiconductive material in the another select gate tier being directly coupled to one another distal the channel material. In one embodiment, horizontally-elongated insulator structures (e.g., 57) extend elevationally through the insulative tiers and the wordline tiers, with the horizontally-elongated insulator structures laterally separating individual wordlines in individual of the wordline tiers.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.