In some embodiments, a memory array comprises a vertical stack comprising a conductive tier, an insulator tier above the conductive tier, and a first stack comprising multiple select gate tiers above the insulator tier. One of the select gate tiers comprise select gate conducting material, and another of the select gate tiers comprise select gate conductor material. The select gate conductor material is vertically thicker than the select gate conducting material. A second stack comprises vertically-alternating insulative tiers and wordline tiers above the first stack. The wordline tiers comprise gate regions of individual memory cells, and individual of the gate regions comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers, the wordline tiers, the one select gate tier, and the another select gate tier and is directly electrically coupled with the conductive material in the conductive tier. The individual memory cells comprise a memory structure between the individual gate regions and the channel material. The memory structure comprises a charge-blocking region laterally inward of the individual gate regions, a storage region laterally inward of individual of the charge-blocking regions, an insulative charge-passage material laterally inward of individual of the storage regions, and a select gate in the one select gate tier and in the another select gate tier. The select gate comprises the conducting material in the one select gate tier and the conductor material in the another select gate tier.