Memory array and methods used in forming a memory array
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ID
ID Boise
摘要
A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.
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An insulator etch-stop tier 13 is above conductive tier 16. Such is shown as comprising insulator material 31, with examples including silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, an insulative metal oxide comprising multiple different metal elements (e.g., Al, Hf, Zr, etc.), silicon nitride, and combinations of such materials. An example thickness for insulator etch-stop tier 13 is from 10 to 40 nanometers.
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