FIG. 10 illustrates an example multi-shot optimization procedure according to embodiments of the present disclosure. While the flow chart depicts a series of sequential steps, unless explicitly stated, no inference should be drawn from that sequence regarding specific order of performance, performance of steps or portions thereof serially rather than concurrently or in an overlapping manner, or performance of the steps depicted exclusively without the occurrence of intervening or intermediate steps. The process depicted in the example depicted is implemented by processor circuitry in, for example, a gNB. Process 900 can be accomplished by, for example, gNB 102, and gNB 103 in network 100.
In the example shown in FIG. 10, a first UE 116 is in a cell of, and in communication with, gNB 102, while a second UE 115 is in a cell of, and in communication with, gNB 103. Each gNB includes, or is coupled with, a respective DU. For example, gNB 102 includes DU1 1005 while gNB 103 includes DU2 1010.
