Three-dimensional memory
地域：
Hsinchu
摘要
Three-dimensional memories are provided. A three-dimensional memory includes a memory cell array, a first interconnect structure, a bit line decoder and a second interconnect structure. The bit line decoder is formed under the memory cell array and the first interconnect structure. The memory cell array includes a plurality of memory cells formed in a plurality of levels stacked in a first direction. The first interconnect structure includes at least one bit line extending in a second direction that is perpendicular to the first direction. The bit line includes a plurality of sub-bit lines stacked in the first direction. Each of the sub-bit lines is coupled to the memory cells that are arranged in a line in the corresponding level of the memory cell array. The second interconnect structure is configured to connect the bit line to the bit line decoder passing through the first interconnect structure.
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A recent trend in semiconductor memories is to fabricate three-dimensional (3D) integrated circuits (3D IC). 3D ICs include a variety of structures, such as die on silicon interposer, stacked dies, multi-tiered, stacked CMOS structures, and the like. These 3D circuits offer a host of advantages over traditional two dimensional circuits: lower power consumption, higher memory cell density, greater efficiency, alleviating bottlenecks, shorter critical path delays, and lower area cost to name just a few.
Shrinking the cell size and increasing density for memory is eagerly needed for various applications, e.g., embedded memory or standalone memory. Therefore, it is important to have a memory with a small size and a high density.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various nodes are not drawn to scale. In fact, the dimensions of the various nodes may be arbitrarily increased or reduced for clarity of discussion.
權(quán)利要求
What is claimed is:1. A three-dimensional memory, comprising:a memory cell array comprising a plurality of memory cells formed in a plurality of levels stacked in a first direction; a first interconnect structure formed on one side of the memory cell array, and comprising:at least one bit line extending in a second direction that is perpendicular to the first direction, wherein the bit line comprises a plurality of sub-bit lines stacked in the first direction, and each of the sub-bit lines is coupled to the memory cells arranged in a line in the corresponding level of the memory cell array; a bit line decoder formed under the memory cell array and the first interconnect structure; and a second interconnect structure configured to connect the bit line to the bit line decoder passing through the first interconnect structure. 2. The three-dimensional memory as claimed in claim 1 , wherein the second interconnect structure comprises:a plurality of first conductive features extending in the first direction, wherein each of the first conductive features is in contact with the corresponding sub-bit line; a plurality of second conductive features formed in a level over the memory cell array and extending in a third direction that is perpendicular to the first and second directions; and a plurality of third conductive features extending in a fourth direction to the bit line decoder passing through the first interconnect structure, wherein the fourth direction is antiparallel to the first direction, wherein the first conductive features are coupled to the third conductive features through the second conductive features. 3. The three-dimensional memory as claimed in claim 2 , wherein the second interconnect structure further comprises:an isolation material formed between the third conductive features and the first interconnect structure. 4. The three-dimensional memory as claimed in claim 1 , wherein the first interconnect structure further comprises:at least one source line extending in the second direction, wherein the source line comprises a plurality of sub-source lines stacked in the first direction, and each of the sub-source lines is coupled to the memory cells arranged in a line in the corresponding level of the memory cell array. 5. The three-dimensional memory as claimed in claim 4 , further comprising:a source line decoder formed under the memory cell array and the first interconnect structure; and a third interconnect structure configured to connect the source line to the source line decoder passing through the first interconnect structure. 6. The three-dimensional memory as claimed in claim 1 , further comprising:a fourth interconnect structure formed on the opposite side of the memory cell array, and comprising:at least one source line extending in the second direction, wherein the source line comprises a plurality of sub-source lines stacked in the first direction, and each of the sub-source lines is coupled to the memory cells that are arranged in a line in the corresponding level of the memory cell array; a source line decoder formed under the memory cell array and the fourth interconnect structure; and a fifth interconnect structure configured to connect the source line to the source line decoder passing through the fourth interconnect structure. 7. The three-dimensional memory as claimed in claim 1 , wherein the second interconnect structure comprises:a plurality of first conductive features extending in the first direction, wherein each of the first conductive features is in contact with the corresponding sub-bit line; a plurality of second conductive features formed in a level over the memory cell array and extending in the second direction; a plurality of third conductive features extending in a third direction to the bit line decoder passing through the first interconnect structure, wherein the third direction is antiparallel to the first direction, wherein the first conductive features are coupled to the third conductive features through the second conductive features. 8. The three-dimensional memory as claimed in claim 7 , wherein the second interconnect structure further comprises:an isolation material formed between the third conductive features and the first interconnect structure. 9. The three-dimensional memory as claimed in claim 1 , further comprising:a plurality of word lines under or over the memory cell array, wherein the word lines extend in a fifth direction that is perpendicular to the first and second directions. 10. A three-dimensional memory, comprising:a semiconductor substrate; a memory cell array formed over a first area of the semiconductor substrate and comprising a plurality of memory cells formed in a plurality of levels stacked in a first direction; a first interconnect structure formed over the first area of the semiconductor substrate and on one side of the memory cell array, and comprising:at least one bit line extending in a second direction that is perpendicular to the first direction, wherein the bit line comprises a plurality of sub-bit lines stacked in the first direction, and each of the sub-bit lines is coupled to the memory cells arranged in a line in the corresponding level of the memory cell array; a bit line decoder formed under the semiconductor substrate; and a second interconnect structure configured to connect the bit line to the bit line decoder passing through a second area of the semiconductor substrate. 11. The three-dimensional memory as claimed in claim 10 , wherein the second interconnect structure comprises:a plurality of first conductive features extending in the first direction, wherein each of the first conductive features is in contact with the corresponding sub-bit line; a plurality of second conductive features formed in a level over the memory cell array; and a plurality of third conductive features extending in a third direction to the bit line decoder passing through the second area of the semiconductor substrate, wherein the third direction is antiparallel to the first direction, wherein the first conductive features are coupled to the third conductive features through the second conductive features. 12. The three-dimensional memory as claimed in claim 11 , wherein the number of the third conductive features is equal to the number of sub-bit lines. 13. The three-dimensional memory as claimed in claim 10 , further comprising:a source line decoder formed under the semiconductor substrate; and a third interconnect structure configured to connect at least one source line of the first interconnect structure to the source line decoder passing through the second area of the semiconductor substrate, wherein the source line extend in the second direction, wherein the source line comprises a plurality of sub-source lines stacked in the first direction, and each of the sub-source lines is coupled to the memory cells arranged in a line in the corresponding level. 14. The three-dimensional memory as claimed in claim 13 , wherein in each of the levels of the memory cell array, the memory cells are arranged in a plurality of lines, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent lines. 15. The three-dimensional memory as claimed in claim 10 , wherein the second interconnect structure comprises:a first sub-structure configured to connect a plurality of sub-bit lines of the bit line to the bit line decoder passing through the second area of the semiconductor substrate; and a second sub-structure configured to connect the remaining sub-bit lines of the bit line to the bit line decoder passing through the second area of the semiconductor substrate. 16. The three-dimensional memory as claimed in claim 15 , wherein each of the first and second sub-structures comprises:a plurality of first conductive features extending in the first direction, wherein each of the first conductive features is in contact with the corresponding sub-bit line; a plurality of second conductive features formed over the memory cell array; and a plurality of third conductive features extending in a third direction to the bit line decoder passing through the second area of the semiconductor substrate, wherein the third direction is antiparallel to the first direction, wherein the first conductive features are coupled to the third conductive features through the second conductive features. 17. The three-dimensional memory as claimed in claim 16 , wherein the second conductive features of the first sub-structure are formed in a first level, and the second conductive features of the second sub-structure are formed in a second level over the first level. 18. A three-dimensional memory, comprising:a semiconductor substrate; a memory cell array formed over a first area of the semiconductor substrate and comprising a plurality of memory cells formed in a plurality of levels stacked in a first direction; a first interconnect structure formed over the first area of the semiconductor substrate on one side of the memory cell array, and comprising:at least one bit line extending in a second direction that is perpendicular to the first direction, wherein the bit line comprises a plurality of sub-bit lines stacked in the first direction, and each of the sub-bit lines is coupled to the memory cells arranged in a line in the corresponding level; a bit line decoder formed under the memory cell array and the first interconnect structure; a second interconnect structure configured to connect a partition of the sub-bit lines of the bit line to the bit line decoder passing through a second area of the semiconductor substrate; and a third interconnect structure configured to connect the remaining sub-bit lines of the bit line to the bit line decoder passing through the first area of the semiconductor substrate. 19. The three-dimensional memory as claimed in claim 18 , wherein the second interconnect structure comprises:a plurality of first conductive features extending in the first direction, wherein each of the first conductive features is in contact with the corresponding sub-bit line; a plurality of second conductive features formed in a first level over the memory cell array; and a plurality of third conductive features extending in a third direction to the bit line decoder passing through the second area of the semiconductor substrate, wherein the third direction is antiparallel to the first direction, wherein the first conductive features are coupled to the third conductive features through the second conductive features. 20. The three-dimensional memory as claimed in claim 19 , wherein the third interconnect structure comprises:a plurality of fourth conductive features extending in the first direction, wherein each of the fourth conductive features is in contact with the corresponding sub-bit line; a plurality of fifth conductive features formed in the first level; and a plurality of sixth conductive features extending in the third direction to the bit line decoder passing through the first interconnect structure at one of the sub-bit lines of the first interconnect structure, wherein the fourth conductive features are coupled to the sixth conductive features through the fifth conductive features, wherein the one of the sub-bit lines has a larger area than the other sub-bit lines.
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