In each of the levels LV0 to LVm, the sub-lines of the lines LN0 to LNx are separated by the sub-bit line or the sub-source line. For example, in the level LV0, the sub-lines LN0_0 and LN1_0 are separated by the sub-source line SL0_0, and the sub-lines LN1_0 and LN2_0 are separated by the sub-bit line BL1_0. Furthermore, in each of the levels LV0 to LVm, the sub-source line is surrounded by the two adjacent sub-lines. Similarly, the sub-bit line is surrounded by the two adjacent sub-lines.

In each of the levels LV0 to LVm, the sub-source line is shared by the memory cells of two adjacent sub-lines, and the sub-bit line is shared by the memory cells of two adjacent sub-lines. For example, in the level LV0, the sub-source line SL0_0 is shared by the memory cells in the sub-lines LN0_0 and LN1_0, and the sub-bit line BL1_0 is shared by the memory cells in the sub-lines LN1_0 and LN2_0.

In the memory cell array of FIG. 2, the lines LN0 to LNx of the memory cells 30 extend in the Y direction. Furthermore, for each of the lines LN0 to LNx, the sub-lines are stacked along a line perpendicular to the plane formed by X direction and Y direction (e.g., Z direction of FIG. 1). For example, the sub-line LN0_0 is the highest line and the sub-line LN0_m is the lowest line in the stacked sub-lines of line LN0.