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Three-dimensional memory

專利號(hào)
US11991887B2
公開日期
2024-05-21
申請(qǐng)人
Taiwan Semiconductor Manufacturing Company, Ltd.（TW Hsinchu）
發(fā)明人
Chenchen Jacob Wang; Chun-Chieh Lu; Yi-Ching Liu
IPC分類
H10B51/40; G11C11/22; G11C16/08; H01L23/522; H10B43/27; H10B43/40; H10B51/20; H10B43/10; H10B51/10
技術(shù)領(lǐng)域
bit,sub,memory,lv0,line,conductive,bl0_0,in,structure,lines
地域： Hsinchu

摘要

Three-dimensional memories are provided. A three-dimensional memory includes a memory cell array, a first interconnect structure, a bit line decoder and a second interconnect structure. The bit line decoder is formed under the memory cell array and the first interconnect structure. The memory cell array includes a plurality of memory cells formed in a plurality of levels stacked in a first direction. The first interconnect structure includes at least one bit line extending in a second direction that is perpendicular to the first direction. The bit line includes a plurality of sub-bit lines stacked in the first direction. Each of the sub-bit lines is coupled to the memory cells that are arranged in a line in the corresponding level of the memory cell array. The second interconnect structure is configured to connect the bit line to the bit line decoder passing through the first interconnect structure.

說明書

In FIG. 3, the channels 220 of the memory cells 30_10 and 30_30 are formed over the word line WL0, and the channels 220 of the memory cells 30_20 and 30_50 are formed over the word line WL1. Therefore, the memory cells 30_10 and 30_30 are aligned with each other, and the memory cells 30_20 and 30_50 are aligned with each other. However, the memory cells 30_10 and 30_30 are not aligned with the memory cells 30_20 and 30_50. i.e., the positions of the memory cells 30_10 and 30_30 and the positions of the memory cells 30_20 and 30_50 are staggered.

In some embodiments, the channel 220 of the memory cell 30_20 in the sub-line LN1_0 is aligned with the dielectric layer 210 in the boundary of the memory cell 30_10 in sub-line LN0_0 and the dielectric layer 210 in the boundary of the memory cell 30_30 in sub-line LN2_0. Furthermore, the channel 220 of the memory cell 30_10 in the sub-line LN0_0 is aligned with the dielectric layer 210 in the boundary of the memory cell 30_20 in the sub-line LN1_0 and the channel of the memory cell 30_30 in the sub-line LN2_0.

權(quán)利要求

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