Three-dimensional memory
摘要
說明書
In some embodiments, the conductive feature 116 may be a second via extending in the Z2 direction and pass through the interconnect structure 20 and the semiconductor substrate 15, so as to connect the transistor MM of the bit line decoder 40. The Z2 direction is antiparallel to the Z1 direction. Furthermore, the conductive features 116 in the conductive paths CON_path are the same length between the conductive features 115 and the bit line decoder 40. In the layout of the interconnect structure 110, the conductive features 116 are arranged in a first line and the conductive features 112 are arranged in a second line parallel to and adjacent the first line.
The conductive feature 116 is separated from the interconnect structure 20 by an isolation material. Therefore, compared with the conductive feature 112 that is in contact with the sub-bit line of the interconnect structure 20, the conductive feature 116 is not in contact with the interconnect structure 20. For each sub-bit line in the levels of the interconnect structure 20, the conductive feature 112 is coupled to the conductive feature 116 through the corresponding conductive feature 115.
