In FIG. 6, the interconnect structures 20 and 50 and the memory cell array 10 are formed over the semiconductor substrate 15, and the interconnect structures 20 and 50 are formed on opposite sides of the memory cell array 10. Moreover, the bit line decoder (e.g., 40 of FIG. 4) and the source line decoder 60 are formed under the semiconductor substrate 15. In other words, the bit line decoder and the source line decoder 60 are CMOS under array (CuA). Moreover, the source line decoder 60 includes multiples transistors MM1 coupled to the corresponding sub-source lines. In some embodiments, the transistors MM1 are planar transistors or fin transistors.

As described above, the interconnect structure 110 is configured to connect the sub-bit lines BL0_0 through BL0_7 of the bit line BL0 from the interconnect structure 20 to the bit line decoder 40 passing through the interconnect structure 20 and the semiconductor substrate 15.

The interconnect structure 130 is configured to connect the sub-source lines SL0_0 through SL0_7 of the bit line SL0 from the interconnect structure 50 to the source line decoder 60 passing through the interconnect structure 50 and the semiconductor substrate 15. Specifically, each of the sub-source lines SL0_0 through SL0_7 in the interconnect structure 50 is coupled to the corresponding transistor MM1 of the source line decoder 60 through respective conductive paths (or hookup structure) in the interconnect structure 130.