In some embodiments, the conductive feature 216 may be a sixth via extending in the Z2 direction and only pass through the semiconductor substrate 15, so as to connect the transistor MM of the bit line decoder 40. The Z2 direction is antiparallel to the Z1 direction. Furthermore, the conductive features 216 are all the same length. In the layout of the interconnect structure 210, the conductive features 216 are arranged in a first line and the conductive features 212 are arranged in a second line. The second line is perpendicular to the first line.

In some embodiments, a source line decoder (not shown) is formed under the semiconductor substrate 15, and an interconnect structure (not shown) is configured to connect the sub-source lines of the interconnect structure 20 to the source line decoder passing through the semiconductor substrate 15. The interconnected structure coupled to the source line decoder has a configuration similar to the interconnect structure 210.

In some embodiments, the source line decoder is formed under the semiconductor substrate 15, and a first interconnect structure (not shown) is formed on opposite sides of the memory cell array 10 and configured to connect the sub-source lines to the memory cell array 10. Moreover, a second interconnect structure (not shown) is formed over the first interconnect structure and is configured to connect the sub-source lines from the first interconnect structure to the source line decoder passing through the semiconductor substrate 15. The first interconnected structure has a configuration similar to the interconnect structure 20, and the second interconnected structure has a configuration similar to the interconnect structure 210.