In the interconnect structure 20 of FIG. 8, the area of the sub-bit line in each level that is not overlapped by the upper layer, is large enough to accommodate the conductive features 212. Thus, the pitch width between the conductive feature 212 is enough to meet IC processing requirements, i.e., it does not affect the critical dimension (CD) of the IC. Furthermore, the pitch width between the two adjacent conductive features 216 needs to be designed to meet IC processing requirements.
FIG. 9 shows a stereoscopic view of a three-dimensional memory 100E, in accordance with some embodiments of the disclosure. The three-dimensional memory 100E of FIG. 9 has a similar configuration to the three-dimensional memory 100D of FIG. 8. The difference between the three-dimensional memory 100D of FIG. 8 and the three-dimensional memory 100E of FIG. 9 is that the sub-bit lines BL0_0 through BL0_7 are coupled to the bit line decoder 40A through the interconnect structures 210a and 210b. For example, the sub-bit lines BL0_0 through BL0_3 are coupled to the bit line decoder 40A through the interconnect structure 210a, and the sub-bit lines BL0_4 through BL0_7 are coupled to the bit line decoder 40A through the interconnect structure 210b.
