Three-dimensional memory
摘要
說明書
The memory cells 30 of the same level in the memory cell array 10 may share the sub-bit line or the sub-source line. Moreover, the memory cells 30 of the different levels in the memory cell array 10 may not share the sub-bit line and the sub-source line.
In some embodiments, the bit lines BL (e.g., sub-bit lines BL0_0-BL0_2, BL1_0-BL1_2 and BL2_0-BL2_2) are coupled to the other circuits through the higher metal layer, and the source lines SL (e.g., sub-source lines SL0_0-SL0_2 and SL1_0-SL1_2) are coupled to the other circuits through the higher metal layer.
The three-dimensional memory 100 further includes multiple word lines (not shown) coupled to the memory cell array 10 through the word line via WL_via. The word lines are coupled between the memory cell array 10 and a word line driver (or decoder) (not shown), and the word lines are configured to provide word line information to the memory cells 30 of the memory cell array 10. In some embodiments, the word lines are formed in the same layer under the memory cell array 10. In some embodiments, the word lines are formed in the same layer over the memory cell array 10. In some embodiments, the memory cells 30 of the different levels in the memory cell array 10 may share the same word line.
