Semiconductor device and method for manufacturing the same
地域：
Hsinchu
摘要
A semiconductor device includes a bottom electrode, a top electrode over the bottom electrode, a switching layer between the bottom electrode and the top electrode, wherein the switching layer is configured to store data, a capping layer in contact with the switching layer, wherein the capping layer is configured to extract active metal ions from the switching layer, an ion reservoir region formed in the capping layer, a diffusion barrier layer between the bottom electrode and the switching layer, wherein the diffusion barrier layer includes palladium (Pd), cobalt (Co), or a combination thereof and is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion layer has a concaved top surface, and a passivation layer covering a portion of the top electrode, and wherein the passivation layer directly contacts a top surface of the switching layer.
說明書
This application is a divisional application of prior-filed U.S. application Ser. No. 15/939,864, filed Mar. 29, 2018.
Resistive random access memory (RRAM) and conductive bridge random access memory (CBRAM) are promising candidates for next generation non-volatile memory technology due to their simple structure and compatibility with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes. The RRAM and CBRAM however, still suffer from degradation of switching window, switching time during cycling.
Aspects of the embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.
權(quán)利要求
What is claimed is:1. A semiconductor device, comprising:a bottom electrode; a top electrode over the bottom electrode; a switching layer between the bottom electrode and the top electrode, wherein the switching layer is configured to store data; a capping layer in contact with the switching layer, wherein the capping layer is configured to extract active metal ions from the switching layer; an ion reservoir region formed in the capping layer; a diffusion barrier layer between the bottom electrode and the switching layer, wherein the diffusion barrier layer comprises palladium (Pd), cobalt (Co), or a combination thereof and is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion barrier layer has a concaved top surface; and a passivation layer covering a portion of the top electrode, and wherein the passivation layer directly contacts a top surface of the switching layer, wherein an upper surface of the bottom electrode has a recess, and the bottom electrode includes an outer portion and an inner portion surrounded by the outer portion, and a lowermost surface of the outer portion is above a top surface of the inner portion. 2. The semiconductor device of claim 1 , wherein a material of the switching layer comprises an ion compound, a covalent compound, an oxide compound, or a semiconductive material. 3. The semiconductor device of claim 2 , wherein the ion compound comprises germanium sulfide (GeS) or germanium antimony tellurium (GeSbTe), the covalent compound comprises arsenic sulfide (AsS), the oxide compound comprises tantalum oxide, silicon oxide, aluminum oxide or titanium oxide, and the semiconductive material comprises amorphous silicon. 4. The semiconductor device of claim 1 , wherein a material of the capping layer comprises a metal or a metal compound, wherein the metal comprises copper, silver, aluminum or nickel, and the metal compound comprises copper tantalum or copper tellurium. 5. The semiconductor device of claim 1 , wherein the passivation layer covers an upper surface and edges of the top electrode. 6. The semiconductor device of claim 1 , wherein the passivation layer is in direct contact with the top electrode, the capping layer, the switching layer, and the diffusion barrier layer. 7. The semiconductor device of claim 1 , wherein the passivation layer is in direct contact with a portion of the diffusion barrier layer. 8. The semiconductor device of claim 1 , wherein the diffusion barrier layer further comprises a metal nitride or a metal alloy. 9. The semiconductor device of claim 8 , wherein the metal nitride comprises tungsten nitride, tantalum tungsten nitride, ruthenium tantalum nitride, tantalum germanium oxynitride (Ta—Ge—(O)N) or a combination thereof, and the metal alloy comprises nickel chromium alloy. 10. A semiconductor device, comprising:a bottom electrode; a top electrode over the bottom electrode; a switching layer between the bottom electrode and the top electrode, wherein the switching layer is configured to store data; a capping layer abutting the switching layer and the top electrode; a diffusion barrier layer, wherein the diffusion barrier layer is less reactive to active metal ions than the bottom electrode, and a bottom surface of the diffusion barrier layer is in physical contact with a top surface of the bottom electrode, and wherein the diffusion barrier layer comprises tungsten nitride, tantalum tungsten nitride, tantalum germanium oxynitride (Ta—Ge—(O)N) or a combination thereof, the diffusion barrier layer is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion barrier layer has a concaved top surface; and a passivation layer covering a portion of the top electrode, wherein the passivation layer directly contacts a top surface of the switching layer, wherein an upper surface of the bottom electrode has a recess, and the bottom electrode includes an outer portion and an inner portion surrounded by the outer portion, and a lowermost surface of the outer portion is above a top surface of the inner portion. 11. The semiconductor device of claim 10 , wherein a material of the switching layer comprises an ion compound, a covalent compound, an oxide compound, or a semiconductive material, wherein the ion compound comprises germanium sulfide (GeS) or germanium antimony tellurium (GeSbTe), the covalent compound comprises arsenic sulfide (AsS), the oxide compound comprises tantalum oxide, silicon oxide, aluminum oxide or titanium oxide, and the semiconductive material comprises amorphous silicon. 12. The semiconductor device of claim 10 , wherein the diffusion barrier layer further comprises a metal, a metal alloy or a combination thereof. 13. The semiconductor device of claim 12 , wherein the metal comprises palladium (Pd), tantalum (Ta), niobium (Nb), cobalt (Co), ruthenium (Ru) or a combination thereof. 14. The semiconductor device of claim 12 , wherein the metal alloy comprises nickel chromium alloy. 15. The semiconductor device of claim 10 , wherein a material of the capping layer comprises a metal or a metal compound, wherein the metal comprises copper, silver, aluminum or nickel, and the metal compound comprises copper tantalum or copper tellurium. 16. A semiconductor device, comprising:a substrate; a metallization layer over the substrate; a bottom electrode, including a metal nitride or a doped semiconductive material; a top electrode, over the bottom electrode; a switching layer, between the bottom electrode and the top electrode, and configured to store data; a capping layer in contact with the switching layer, wherein the capping layer is configured to extract active metal ions from the switching layer; an ion reservoir region formed in the capping layer; a diffusion barrier layer, between the bottom electrode and the switching layer, wherein the diffusion barrier layer comprises tungsten nitride, tantalum tungsten nitride, tantalum germanium oxynitride (Ta—Ge—(O)N) or a combination thereof, the diffusion barrier layer is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion barrier layer has a concaved top surface; and a passivation layer, covering a portion of the top electrode, wherein the bottom electrode comprises: an inner portion between a lowermost surface of the diffusion barrier layer and a top surface of the metallization layer; and an outer portion, wherein a lowermost surface of the outer portion is above a top surface of the inner portion. 17. The semiconductor device of claim 16 , wherein the passivation layer directly contacts a top surface of the switching layer. 18. The semiconductor device of claim 16 , wherein a material of the switching layer comprises an ion compound, a covalent compound, an oxide compound, or a semiconductive material. 19. The semiconductor device of claim 18 , wherein the ion compound comprises germanium sulfide (GeS) or germanium antimony tellurium (GeSbTe), the covalent compound comprises arsenic sulfide (AsS), the oxide compound comprises tantalum oxide, silicon oxide, aluminum oxide or titanium oxide, and the semiconductive material comprises amorphous silicon. 20. The semiconductor device of claim 16 , wherein the diffusion barrier layer further comprises a metal, a metal alloy or a combination thereof.
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