FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, FIG. 6E, FIG. 6F and FIG. 6G are schematic views at one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. As shown in FIG. 6A, a substrate 10 is received. In some embodiments, a bottom interconnect structure 32 may be formed over the substrate 10. In some embodiments, the bottom interconnect structure 32 includes a bottom metallization layer 321, and a bottom inter-layer dielectric (ILD) layer 322 laterally surrounding the bottom metallization layer 121. In some embodiments, the bottom metallization layer 321 may be one layer of the back-end-of-the line (BEOL). In some embodiments, the material of the bottom metallization layer 321 may include metal or alloy such as copper, tungsten, alloy thereof or the like. The material of the bottom ILD layer 322 may include dielectric material such as low-k dielectric material with a dielectric constant less than 2.0 or the like, but is not limited thereto.

As shown in FIG. 6B, a dielectric layer 34 is formed over the substrate 10. In some embodiments, the dielectric layer 34 is formed over the bottom interconnect structure 32 and includes an opening 34R exposing a portion of the bottom metallization layer 321. In some embodiments, the material of the dielectric layer 34 may include dielectric material such as silicon oxide, silicon nitride, silicon oxynitride or the like.