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Method of manufacturing a memory device comprising introducing a dopant into silicon oxide

專利號
US11991939B2
公開日期
2024-05-21
申請人
Kioxia Corporation(JP Tokyo)
發(fā)明人
Yoshinori Kumura
IPC分類
H10N70/00; H10B61/00; H01L29/36
技術領域
variable,resistance,dopant,material,electrode,in,memory,ibe,32b,conductor
地域: Tokyo

摘要

According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.

說明書

In the specification and the claims, a phrase of a particular first component being “coupled” to another second component includes the first component being coupled to the second component either directly or via one or more components which are always or selectively conductive.

The embodiments will be described by using an xyz orthogonal coordinate system.

In the description below, the term “below” as well as terms derived therefrom and terms related thereto refer to a position having a smaller coordinate on the z-axis, and the term “above” as well as terms derived therefrom and terms related thereto refer to a position having a larger coordinate on the z-axis.

First Embodiment

<1. Structure (Configuration)>

<1.1. Overall Structure>

FIG. 1 illustrates functional blocks of memory device of the first embodiment. As shown in FIG. 1, a memory device 1 includes a memory cell array 11, an input and output circuit 12, a control circuit 13, a row selection circuit 14, a column selection circuit 15, a write circuit 16, and a read circuit 17.

The memory cell array 11 includes memory cells MC, word lines WL, and bit lines BL. The memory cell MC can store data in a non-volatile manner. Each memory cell MC is coupled to one word line WL and one bit line BL. Each word line WL is associated with a row. Each bit line BL is associated with a column. Selection of one row and selection of one or more columns specify one or more memory cells MC.

權利要求

1
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