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Adaptive timing for high frequency inverters

專利號
US11996767B1
公開日期
2024-05-28
申請人
Apple Inc.(US CA Cupertino)
發(fā)明人
Weihong Qiu; Jun Liu; Jizhen Fu; Zaki Moussaoui
IPC分類
H02M1/08; H02J50/10; H02M1/38; H02M7/5387; H02M7/5395
技術(shù)領(lǐng)域
dead,switching,inverter,voltage,vsw,comparator,time,gate1,gate2,switch
地域: CA CA Cupertino

摘要

A method of adaptively controlling dead time between turn off of a first switching device of an inverter and turn on of a second switching device of the inverter that is a counterpart of the first switching device can include: monitoring a plurality of switching events of at least one of the first and second switching devices, storing for each monitored switching event an indication whether a dead time associated therewith permitted optimal switching, and adaptively controlling the dead time responsive to the stored indications. Monitoring a plurality of switching events of at least one of the first and second switching devices can further include sampling an output voltage of the inverter and comparing the sampled output voltage to one of a high reference voltage corresponding to a high inverter rail voltage and a low reference voltage corresponding to a low inverter rail voltage.

說明書

FIG. 2 illustrates a schematic diagram of an inverter 114, as may be used in a wireless power transmitter (PTx) of a wireless power transfer system. The illustrated inverter is a half bridge inverter, so named because the switching devices Q1 and Q2 form a half bridge that selectively couples input DC voltage Vin or ground to the switching node Vsw, thus generating an alternating voltage at this terminal. Switches Q1 and Q2 are illustrated as n-channel MOSFETs, although other suitable switching devices, including but not limited to p-channel MOSFETs could also be used. Switches Q1 and Q2 may be driven substantially complementarily, so that when Q1 is turned on (via a drive signal applied to Gate1), Q2 is turned off (via a drive signal applied to Gate2), and vice versa. The drive of switches Q1 and Q2 is “substantially” complementarily, as a short dead time may be provided at each switching transition to ensure that the switch being turned off before the counterpart switch is turned on. This can prevent short circuiting the input voltage. Additionally, controlling the timing of the switching transitions (e.g., switching frequency, duty cycle, etc.) can be used to control the output voltage (and thus the power delivered) by the inverter.

權(quán)利要求

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