FIG. 3A illustrates a plot 300a of waveforms associated with an inverter, such as the half bridge inverter 114 illustrated in FIG. 2 featuring “optimal” dead times at the switching transitions. Plot 300a includes Vsw—the “output” of the inverter (i.e., the voltage appearing at terminal Vsw), Gate1, which is the gate drive signal for upper switch Q1, and Gate2, which is the gate drive signal for lower switch Q2. FIG. 3A illustrates the switching transitions associated with a single switching cycle. Thus, beginning just before time t0, Gate1 is low, meaning switch Q1 is turned off, and Gate2 is high, meaning switch Q2 is turned on. As a result, the node Vsw is coupled to ground, and the output voltage is 0V. At time t0, Gate2 transitions low, turning off lower switch Q2 and initiating a first dead time Tdt1 during which both switches are turned off. During this interval, the output voltage Vsw climbs to a value Vin at time t1. This indicates the end of the dead time, when Gate1 transitions high, turning on upper switch Q1. At time t2 (determined by the inverter controller) Gate1 transitions low again, turning off upper switch Q1. This commences second dead time Tdt2. During this interval output voltage Vsw decreases to 0V at time t3, marking the end of the dead time Tdt2, and the point at which Gate2 transitions high, turning on switch Q2. At each turn on switching transition, the voltage across the switch turning on is the same before and after the switching event, which can be described as “zero-voltage switching (ZVS).”