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Adaptive timing for high frequency inverters

專利號
US11996767B1
公開日期
2024-05-28
申請人
Apple Inc.（US CA Cupertino）
發(fā)明人
Weihong Qiu; Jun Liu; Jizhen Fu; Zaki Moussaoui
IPC分類
H02M1/08; H02J50/10; H02M1/38; H02M7/5387; H02M7/5395
技術(shù)領(lǐng)域
dead,switching,inverter,voltage,vsw,comparator,time,gate1,gate2,switch
地域： CA CA Cupertino

摘要

A method of adaptively controlling dead time between turn off of a first switching device of an inverter and turn on of a second switching device of the inverter that is a counterpart of the first switching device can include: monitoring a plurality of switching events of at least one of the first and second switching devices, storing for each monitored switching event an indication whether a dead time associated therewith permitted optimal switching, and adaptively controlling the dead time responsive to the stored indications. Monitoring a plurality of switching events of at least one of the first and second switching devices can further include sampling an output voltage of the inverter and comparing the sampled output voltage to one of a high reference voltage corresponding to a high inverter rail voltage and a low reference voltage corresponding to a low inverter rail voltage.

說明書

At root, part of the problem with operating at increasingly high frequencies is that the comparators (or equivalent circuitry) that monitor the output voltage Vsw to determine whether it has reached a “target” value that will allow zero-voltage switching have speed limits. In other words, the comparators only operate so fast. While it is possible to use ever faster comparator circuitry, this can introduce undesired costs, etc. An alternative approach is illustrated in FIG. 5, which includes a sample and hold comparator circuit 500. In sample and hold comparator circuit 500, comparator 503 can be a more “standard” comparator, i.e., not necessarily a high-speed comparator.

權(quán)利要求

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