Beginning just before time t0, Gate2 is high, corresponding to lower switch Q2 being turned on. Gate1 is low, corresponding to upper switch Q1 being turned off. Output voltage Vsw is zero (because Q2 is turned on, coupling the Vsw terminal to ground). As described above, at time t0 Gate2 transitions low, turning off lower switch Q2 and commencing dead time Tdt1. At some time shortly thereafter (but before t1), switch Sd0 may be turned on, allowing the sample and hold circuit coupled to the non-inverting input of comparator 503 to begin sampling output voltage Vsw. Likewise, switch S1 can be turned on, allowing the sample and hold circuit coupled to the inverting input of comparator 503 to begin sampling the “high” reference voltage corresponding to the DC rail voltage Vin. Switches S0 and S1 may be turned off at time t1, just prior to Gate1 transitioning high, turning on high upper switch Q1. This “l(fā)ocks in” the sample value Vsh corresponding to the value of Vsw just prior to the switching transition.