As noted above, at time t4, Gate1 can transition low, turning off upper switch Q1 and beginning dead time Tdt2. After time t4, switches S0 and S2 can be turned on, allowing the sample and hold circuit coupled to the non-inverting input of comparator 503 to sample the inverter output voltage Vsw and the sample and hold circuit coupled to the inverting input of comparator 503 to sample the low reference voltage. Switches S0 and S2 can be turned off at time t5, prior to time t6 at which Gate2 transitions high, turning on low switch Q2. This “l(fā)ocks in” the sample value Vsh corresponding to the value of Vsw just prior to the switching transition.

Following time t6, Gate2 is high, meaning that lower switch Q2 is turned on, and voltage Vsw is at the low voltage (ground) corresponding to the inverter's lower rail voltage. During this interval, comparator 503 (which may be a relatively slow comparator) can perform a comparison of the sample Vsh corresponding to the inverter output voltage Vsw just prior to lower switch Q2 turning on. Because comparator 503 may be relatively slow, the comparator output voltage Vcmp may take a relatively long time to transition, as illustrated by slopes 644/645. If there is a sharp voltage transition 642, indicating that dead time Tdt2 is too short, then the comparator output (Vcmp) will be high (as will be a corresponding sample SW_ZVS of the comparator output, taken as described below). Otherwise, then dead time Tdt2 is not too long, and the comparator output (Vcmp) will be zero (as will be a corresponding sample SW_ZXVS of the comparator output, taken as described below).