FIG. 8A illustrates a plot 800a of the inverter output Vsw (851a), the upper switch dead time for each switching cycle (852a), and the lower switch dead time for each switching cycle (853a) when implementing the above-described adaptive dead time control. As can be seen at the beginning both upper and lower switches ay exhibit a relatively long dead time, with such dead time being too long to allow for suitable switching. Over time, an adaptive controller as described above may continually decrease the dead time (852a/853a) until suitable switching is achieved, at which point the dead time values will hold relatively constant (as indicated in the right-hand portion of FIG. 8A). FIG. 8B illustrates plot 800b corresponding to a single switching cycle with a too long dead time, as in the left-hand portion of FIG. 8A. The upper switch dead time 852b and lower switch dead time 853b are shown as constant over the single switching cycle and decremented at the end of the switching cycle because of the non-zero voltage switching transitions indicating by overshoots 841 and 842 of inverter output voltage 851b. FIG. 8C illustrates plot 800c corresponding to an optimal dead time, as in the right-hand portion of FIG. 8A. The upper switch dead time 852c and lower switch dead time 853c are shown as constant over the single switching cycle and do not change at the end of the switching cycle because suitable switching was achieved, as indicated by the absence of overshoots or undershoots in the output voltage waveform 851c.