FIG. 2, FIG. 5, FIG. 8, FIG. 10, FIG. 11, FIG. 33, FIG. 35 and FIG. 36 illustrate the realizations in which a capacitor device 3 connected in parallel with said voltage source 1 through said first T1 and second T2 output terminals of said capacitor device 3 and an additional switching device 7 in on state.
FIG. 3, FIG. 12, FIG. 13, FIG. 14, FIG. 17, FIG. 20, FIG. 34 and FIG. 37 illustrate the realizations in which a capacitor device 3 connected in parallel with said voltage source 1 through said first T1 and second T2 output terminals of said capacitor device 3 and a first 7 and a second 9 additional switching devices in on state;