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Digital compensation system for a radio frequency power amplifier module

專利號
US11996810B2
公開日期
2024-05-28
申請人
Qorvo US, Inc.(US NC Greensboro)
發(fā)明人
Frederick L. Martin; Gangadhar Burra; Nikolaus Klemmer; Paul Edward Gorday; Bror Peterson
IPC分類
H03F3/24; H03F1/02; H03F3/195
技術領域
amplifier,rf,bias,envelope,signal,digital,gan,dpd,baseband,output
地域: NC NC Greensboro

摘要

A digital compensation system for a radio frequency (RF) power amplifier module is disclosed. The digital compensation system includes an RF power amplifier having a first input, a first output, and a first bias input, wherein the RF power amplifier is configured to receive an RF signal at the first input and generate an amplified version of the RF signal at the first output. The digital compensation system also includes compensation circuitry coupled between the first input and the first output and a bias output coupled to the RF power amplifier, wherein the compensation circuitry is configured, in response to the RF signal, to generate or adjust a bias signal at the first bias input to correct dynamic bias errors caused by amplification variations that have time constants.

說明書

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

A loop filter output, f(n), is converted to an analog bias adjustment signal, vb(t), using a digital-to-analog converter (DAC) 40. The analog bias adjustment signal, vb(t), is applied to bias the RF amplifier 12. The polarity of the bias adjustment is such that vb(t) acts to reduce the bias error. As such, digital compensation system 10 is a closed-loop feedback control type system that realizes the objective to mitigate bias errors and thereby minimize variations in gain and linearity characteristics of the RF amplifier 12. The input coupler 14, the output 16, the input envelope detector 18, the output envelope detector 20, the IN_ADC 22, the OUT_ADC 24, the processor 26, and the DAC 40 make up compensation circuitry 42.

權利要求

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