The compensation system 10 is expected to be complimentary to a wideband digital pre-distorter (DPD) 44 used to linearize the RF amplifier 12, as shown in FIG. 5. In at least some embodiments, the compensation settling period Tsettle is as short as practical. Specifically, the bandwidth of the input envelope detector 18 and the output envelope detector 20, along with the sampling rates of the IN_ADC 22, the OUT_ADC 24, and the DAC 40, determine the duration of the compensation settling period Tsettle. As depicted in FIG. 5, a compensation circuitry 42 operates as an inner loop to quickly correct any sudden bias errors caused by amplification variations that have time constants, while the DPD 44 acts as a slower outer loop to correct for amplifier nonlinearity. Typical DPD implementations compute their coefficients based on observation periods (blocks) lasting tens of microseconds. The compensation settling period Tsettle is smaller than a DPD block duration, Tdpd, in order to minimize effects of the bias errors on DPD coefficient calculations. Amplification variations that have time constants include but are not limited to amplification gain fluctuations due to charge trapping and amplifier gain fluctuations due to temperature changes.
The 3-dB bandwidth for the envelope detectors is Be=fs/10, where fs is the ADC/DAC sampling rate. This provides good suppression to aliasing in the ADC sampling process.
