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Thin film transistors with spacer controlled gate length

專利號(hào)
US11997847B2
公開日期
2024-05-28
申請(qǐng)人
Intel Corporation（US CA Santa Clara）
發(fā)明人
Abhishek A. Sharma; Van H. Le; Gilbert Dewey; Shriram Shivaraman; Yih Wang; Tahir Ghani; Jack T. Kavalieros
IPC分類
H01L29/417; H01L29/45; H01L29/49; H01L29/51; H01L29/66; H01L29/786; H10B12/00
技術(shù)領(lǐng)域
electrode,tft,spacer,gate,may,dielectric,drain,layer,source,in
地域： CA CA Santa Clara

摘要

Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

說明書

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of U.S. patent application Ser. No. 16/473,592 which is a national phase entry under 35 U.S.C. § 371 of International Application No. PCT/US2017/025593, filed Mar. 31, 2017, entitled “THIN FILM TRANSISTORS WITH SPACER CONTROLLED GATE LENGTH”, which designated, among the various States, the United States of America. The Specifications of the PCT/US2017/025593 and Ser. No. 16/473,592 Applications are hereby incorporated by reference in their entirety.

FIELD

Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to transistors.

BACKGROUND

A thin-film transistor (TFT) is a kind of field-effect transistor including a channel layer, a gate electrode, and source and drain electrodes, over a supporting but non-conducting substrate. A TFT differs from a conventional transistor, where a channel of the conventional transistor is typically within a substrate, such as a silicon substrate. TFTs have emerged as an attractive option to fuel Moore's law by integrating TFTs vertically in the back-end, while leaving the silicon substrate areas for high-speed transistors. TFTs hold great potential for large area and flexible electronics, e.g., displays. Other applications of TFTs may include memory arrays.

權(quán)利要求

1
What is claimed is:1. A method for forming a thin film transistor (TFT), the method comprising:forming a gate electrode above a substrate;forming a gate dielectric layer conformally covering the gate electrode and the substrate;forming a channel layer above the gate dielectric layer;forming a source electrode above the channel layer, wherein the source electrode is separated from another source electrode of an adjacent transistor by a pitch, and the source electrode has a first width;subsequent to forming the source electrode, forming a spacer next to the source electrode and above the channel layer, wherein the spacer has a second width, and overlaps with the gate electrode; andsubsequent to forming the spacer, forming a drain electrode next to the spacer and above the channel layer, wherein the drain electrode has a third width, and wherein a sum of the first width, the second width, and the third width is less than the pitch.2. The method of claim 1, wherein the source electrode is a first source electrode, the spacer is a first spacer, and the method further comprising:forming a second source electrode above the channel layer, wherein the second source electrode is separated from the first source electrode by the pitch; andforming a second spacer between the drain electrode and the second source electrode and above the channel layer.3. The method of claim 1, wherein the second width is about 5% to 15% of the first width.4. The method of claim 1, wherein the source electrode includes a first conductive material, and the drain electrode includes a second conductive material different from the first conductive material.5. The method of claim 1, wherein the first width is different from the third width.6. The method of claim 1, further comprising:forming a top dielectric layer above the source electrode, the drain electrode, and the spacer, wherein the spacer includes a first dielectric material, and the top dielectric layer includes a second dielectric material different from the first dielectric material.7. The method of claim 1, wherein the gate dielectric layer includes silicon and oxygen, silicon and nitrogen, yttrium and oxygen,silicon, oxygen, and nitrogen, aluminum and oxygen, hafnium and oxygen, tantalum and oxygen, or titanium and oxygen.8. The method of claim 1, wherein the channel layer includes amorphous silicon, zinc (Zn), or oxygen (O).9. The method of claim 1, wherein the source electrode or the drain electrode includes gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir—Ta), or indium-tin oxide (ITO).10. The method of claim 1, wherein a top surface of the spacer and a top surface of the source electrode are level with each other.11. The method of claim 1, wherein the second width of the spacer determines a gate length (Lg) of the gate electrode.
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