Thin film transistors with spacer controlled gate length
摘要
說明書
Embodiments herein may present a computing device, which may include a circuit board, and a memory device coupled to the circuit board and including a memory array. In more detail, the memory array may include a plurality of memory cells. A memory cell of the plurality of memory cells may include a transistor and a storage cell. The transistor in the memory cell may include a gate electrode coupled to a word line of the memory array, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer, where the source electrode, the drain electrode, and the spacer are above the channel layer. In addition, the source electrode may be coupled to a source line of the memory array, the drain electrode may be coupled to the storage cell, and the storage cell may be coupled to a bit line of the memory array. The drain electrode may be separated from the source electrode by the spacer, and the spacer may overlap with the gate electrode. In embodiments, the source electrode may have a first width, and the drain electrode may have a second width different from the first width.
