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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專(zhuān)利號(hào)
US11997853B1
公開(kāi)日期
2024-05-28
申請(qǐng)人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類(lèi)
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說(shuō)明書(shū)

CLAIM FOR PRIORITY

This application is a Continuation of, and claims the benefit of priority to U.S. patent application Ser. No. 17/653,811, filed Mar. 7, 2022, and which is incorporated by reference in its entirety.

BACKGROUND

The standard memory used in processors is static random-access memory (SRAM) or dynamic random-access memory (DRAM), and their derivatives. These memories are volatile memories. For example, when power to the memories is turned off, the memories lose their stored data. Non-volatile memories are now commonly used in computing platforms to replace magnetic hard disks. Non-volatile memories retain their stored data for prolonged periods (e.g., months, years, or forever) even when power to those memories is turned off. Examples of non-volatile memories are magnetic random-access memory (MRAM), NAND, or NOR flash memories. These memories may not be suitable for low power and compact computing devices because these memories suffer from high write energy, low density, and high-power consumption.

Some memories and/or circuits may use multiple capacitors. These capacitors can occupy large areas making them challenging to use as circuit and memory dimensions are reducing.

The background description provided here is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated here, the material described in this section is not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

BRIEF DESCRIPTION OF THE DRAWINGS

權(quán)利要求

1
We claim:1. An apparatus comprising:a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node; anda plurality of capacitors having a first terminal coupled to the storage node via a metal layer, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are planar capacitors that are arranged in a staggered configuration on the metal layer such that a first capacitor of the plurality of capacitors is offset along a horizontal plane diagonally from a second capacitor of the plurality of capacitors.2. The apparatus of claim 1, wherein the metal layer is a shared bottom electrode for the plurality of capacitors.3. The apparatus of claim 1, wherein the plurality of capacitors is staggered in rows.4. The apparatus of claim 1, wherein the metal layer comprises metal, a first conducting oxide, or a combination of a second conducting oxide and an insulative material.5. The apparatus of claim 1, wherein the individual capacitor includes a top electrode which is coupled to the individual plate-line.6. The apparatus of claim 5, wherein the top electrode is coupled to the individual plate-line via a pedestal.7. The apparatus of claim 6, wherein the metal layer is a shared bottom electrode for the plurality of capacitors, wherein the individual capacitor includes:a first layer coupled to the shared bottom electrode which is coupled to the storage node, wherein the first layer comprises a first refractive inter-metallic material, and wherein the first layer extends along an x-plane;a second layer on the first layer, wherein the second layer comprises a first conductive oxide, and wherein the second layer extends along the x-plane;a third layer comprising non-linear polar material, wherein the third layer is on the second layer, and wherein the third layer extends along the x-plane;a fourth layer on the third layer, wherein the fourth layer comprises a second conductive oxide, and wherein the fourth layer extends along the x-plane; anda fifth layer on the fourth layer, wherein the fifth layer comprises a second refractive inter-metallic material, and wherein the individual plate-line is coupled to the fifth layer.8. The apparatus of claim 7, wherein:the first refractive inter-metallic material and the second refractive inter-metallic material include one or more of: Ta, Ti, Al, W, Ni, Ga, Mn, Fe, B, C, N, or Co; andthe first conductive oxide and the second conductive oxide include one or more of: Ir, In, Fe, Ru, Pd, Os, or Re, wherein the apparatus comprises a sixth layer extending along a y-plane, wherein the sixth layer is adjacent to side walls of the first layer, the second layer, the third layer, and the fourth layer, and wherein the sixth layer includes one of: Ti—Al—O, Al2O3, or MgO.9. The apparatus of claim 6, wherein the metal layer is a shared bottom electrode for the plurality of capacitors, wherein the individual capacitor includes:a first layer coupled to the shared bottom electrode which is coupled to the storage node, wherein the first layer comprises a first conductive oxide, and wherein the first layer extends along an x-plane;a second layer comprising non-linear polar material, wherein the second layer is on the first layer, and wherein the second layer extends along the x-plane; anda third layer on the second layer, wherein the third layer comprises a second conductive oxide, wherein the third layer extends along the x-plane, and wherein the individual plate-line is coupled to the third layer.10. The apparatus of claim 1, wherein the individual plate-line is parallel to the bit-line.11. The apparatus of claim 1, wherein the plurality of capacitors comprises non-linear polar material.12. An apparatus comprising:a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node; anda plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, wherein the plurality of capacitors are planar capacitors that are arranged in a stacked and folded configuration, wherein the plurality of capacitors include a first capacitor and a second capacitor, wherein the first capacitor occupies a first region, wherein the second capacitor occupies a second region, and wherein there is an offset between the first region and the second region such that the first region is laterally offset from the second region.13. The apparatus of claim 12, wherein the offset is substantially equal to a lateral length of the first capacitor, and wherein the first region is below the second region.14. The apparatus of claim 12, wherein the offset is less than a lateral length of the first capacitor such that the first region overlaps with the second region.15. The apparatus of claim 12, wherein the storage node extends vertically using vias and metal layers, and wherein the storage node is a point of fold in the stacked and folded configuration.16. The apparatus of claim 15, wherein the plurality of capacitors has N capacitors are divided in L number of stacked layers such that there are N/L capacitors in an individual stacked layer.17. The apparatus of claim 16, wherein the N/L capacitors are shorted together with an electrode.18. An apparatus comprising:a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node;a vertical stack of vias which is coupled to the storage node;a plurality of metal layers which is coupled to the vertical stack of vias; anda plurality of capacitors having a first terminal coupled to the plurality of metal layers, wherein the plurality of capacitors includes capacitors on either side of the vertical stack of vias, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, wherein the plurality of capacitors are planar capacitors, wherein the plurality of capacitors include a first capacitor and a second capacitor, wherein the first capacitor occupies a first region, wherein the second capacitor occupies a second region, and wherein the first region has an offset relative to the second region such that the first region is laterally offset from the second region.19. The apparatus of claim 18, wherein the offset is substantially equal to a lateral length of the first capacitor, and wherein the first region is below the second region.20. The apparatus of claim 18, wherein the offset is less than a lateral length of the first capacitor such that the first region overlaps with the second region.21. The apparatus of claim 18, wherein the storage node extends vertically using vias and metal layers, and wherein the storage node is a point of fold.22. An apparatus comprising:a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node;a metal plane coupled to the storage node through a via; anda plurality of capacitors having bottom electrodes coupled to the metal plane, wherein an individual capacitor of the plurality of capacitors has a top electrode which is coupled to an individual plate-line, wherein the plurality of capacitors are planar capacitors that are arranged in a staggered configuration on the metal plane such that a first capacitor of the plurality of capacitors is offset along the metal plane diagonally from a second capacitor of the plurality of capacitors, and wherein the first capacitor and the second capacitor are on the metal plane.23. The apparatus of claim 22, wherein the top electrode is coupled to the individual plate-line via a pedestal.
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