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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號(hào)
US11997853B1
公開(kāi)日期
2024-05-28
申請(qǐng)人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說(shuō)明書(shū)

FIG. 12C illustrates timing diagram 1230 for write operation for 1TnC bit-cells with plate-line parallel to the word-line, where the write operation involves word-line boosting, in accordance with some embodiments. In this case, PLs are parallel to the WL. Depending on whether logic 1 (Write 1) or logic 0 (Write 0) is being written to the selected capacitor with non-linear polar material, BL, or PL (e.g., BLx and PL0_1) associated with that capacitor of the bit-cell (e.g., 14010,0) is asserted from 0V to Vdd (power supply level). Other WLs or PLs not part of the bit-cell are forced to 0V. In some embodiments, other PLs (e.g., PL0_2, PL0_3, . . . PL0_n) of the selected bit-cell (e.g., 14010,0) are set between 0 and Vdd (e.g., Vdd/2). In some embodiments, PL of the unselected bit-cells (e.g., PL1_0, . . . PL1_n to PLm_0, . . . PLm_n) are set to 0V. In some embodiments, the WLs for the unselected bit-cells (e.g., WL1, WL2, . . . WLm) are set to 0V.

In various embodiments, write operation begins when WL is asserted and boosted above Vdd. The boost level is Vboost which may be 10-50% of Vdd. In one example, Vboost is about 1× to 1.5× of a threshold voltage (Vt) of transistor MN of the 1T1C bit-cell. Since, the select transistor in these configurations is an n-channel device, it is good at passing the 0V and signals closer to it. The signal applied through the BL however, when it is at Vdd, may not pass through the transistor MN1 in completeness. As such, there is a Vt drop across the n-type transistor MN1 if the WL is driven to Vdd. To help get the full range of signaling across the FE capacitor Cfe1, WL-boosting helps negate the Vt drop across the transistor such that BL when driven to Vdd, internal node will also see Vdd, as opposed to Vdd?Vt.

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